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Publications of Author

1. Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong
   A cycle accurate power estimation tool. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:867-870 [Conf]
   
2. Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel
   Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:871-878 [Conf]
   
3. Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse
   The Titanic: what went wrong! [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:349-350 [Conf]
   
4. Stephen D. Posluszny, N. Aoki, D. Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
   "Timing closure by design, " a high frequency microprocessor design methodology. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:712-717 [Conf]
   
5. Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang
   Cell Processor Low-Power Design Methodology. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2005, v:25, n:6, pp:71-78 [Journal]
   
6. Stephen D. Posluszny
   SLS: An Advanced Symbolic Layout System for Bipolar and FET Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:450-458 [Journal]