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Madhav P. Desai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Maryam Shojaei Baghini, Madhav P. Desai
    Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:317-324 [Conf]
  2. Madhav P. Desai, Radenko Cvijetic, James Jensen
    Sizing of Clock Distribution Networks for High Performance CPU Chips. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:389-394 [Conf]
  3. Madhav P. Desai, Yao-Tsung Yen
    A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:125-130 [Conf]
  4. Nevine Nassif, Madhav P. Desai, Dale H. Hall
    Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:230-235 [Conf]
  5. Rupesh S. Shelar, Madhav P. Desai, H. Narayanan
    Decomposition of Finite State Machines for Area, Delay Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:620-625 [Conf]
  6. Maryam Shojaei Baghini, Madhav P. Desai
    Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:317-0 [Conf]
  7. Shabbir H. Batterywala, Madhav P. Desai
    Variance Reduction in Monte Carlo Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:85-90 [Conf]
  8. B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai
    A State Assignment Scheme Targeting Performance and Area. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:378-383 [Conf]
  9. G. Hazari, Madhav P. Desai, A. Gupta, S. Chakraborty
    A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:565-570 [Conf]
  10. Aditya Mittal, Madhav P. Desai
    A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:571-0 [Conf]
  11. Nihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao
    Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:479-0 [Conf]
  12. Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
    Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:99-104 [Conf]
  13. Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai
    An On-Chip Coupling Capacitance Measurement Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:495-499 [Conf]
  14. Vani Prasad, Madhav P. Desai
    Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:417-422 [Conf]
  15. Vani Prasad, Madhav P. Desai
    On Buffering Schemes for Long Multi-Layer Nets. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:455-0 [Conf]
  16. Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
    Inductance Characterization of Small Interconnects Using Test-Signal Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:376-0 [Conf]
  17. Gaurav Trivedi, Madhav P. Desai, H. Narayanan
    Fast DC Analysis and Its Application to Combinatorial Optimization Problems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:695-700 [Conf]
  18. G. Hazari, Madhav P. Desai, H. Kasture
    On the Impact of Address Space Assignment on Performance in Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:540-545 [Conf]
  19. Gaurav Trivedi, Madhav P. Desai, H. Narayanan
    Parallelization of DC Analysis through Multiport Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:863-868 [Conf]
  20. Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai
    AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:245-250 [Conf]
  21. Madhav P. Desai, D. Manjunath
    On Range Matrices and Wireless Networks in d Dimensions. [Citation Graph (0, 0)][DBLP]
    WiOpt, 2005, pp:190-196 [Conf]
  22. Madhav P. Desai, H. Narayanan, Sachin B. Patkar
    The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2003, v:131, n:2, pp:299-310 [Journal]
  23. Nihar R. Mohapatra, A. Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao
    Sub-100 nm CMOS circuit performance with high-K gate dielectrics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:7, pp:1045-1048 [Journal]

  24. Learning based address mapping for improving the performance of memory subsystems. [Citation Graph (, )][DBLP]


  25. Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. [Citation Graph (, )][DBLP]


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