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Shankar Balachandran: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
    On Routing Demand and Congestion Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:639-646 [Conf]
  2. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    On metrics for comparing routability estimation methods for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:70-75 [Conf]
  3. Shankar Balachandran, Dinesh Bhatia
    Timing Aware Interconnect Prediction Models for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:167-172 [Conf]
  4. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:37-47 [Conf]
  5. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    Rapid and Reliable Routability Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:242-252 [Conf]
  6. Shankar Balachandran, Dinesh Bhatia
    A-priori wirelength and interconnect estimation based on circuit characteristics. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:77-84 [Conf]
  7. Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
    On Routing Demand and Congestion Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:639-646 [Conf]
  8. Shankar Balachandran, Dinesh Bhatia
    A priori wirelength and interconnect estimation based on circuit characteristic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1054-1065 [Journal]
  9. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    On metrics for comparing interconnect estimation methods for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:381-385 [Journal]

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