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Dinesh Bhatia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
    On Routing Demand and Congestion Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:639-646 [Conf]
  2. Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
    Exploiting temporal idleness to reduce leakage power in programmable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:651-656 [Conf]
  3. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    On metrics for comparing routability estimation methods for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:70-75 [Conf]
  4. Karthikeya M. Gajjala Purna, Dinesh Bhatia
    Temporal Partitioning and Scheduling for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:329-330 [Conf]
  5. John M. Emmert, Dinesh Bhatia
    A Methodology for Fast FPGA Floorplanning. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:47-56 [Conf]
  6. Jianzhong Shi, Dinesh Bhatia
    Performance Driven Floorplanning for FPGA Based Designs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:112-118 [Conf]
  7. Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna
    REACT: Reactive Environment for Runtime Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:209-217 [Conf]
  8. Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan
    NEBULA: A Partially and Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:405-410 [Conf]
  9. Shankar Balachandran, Dinesh Bhatia
    Timing Aware Interconnect Prediction Models for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:167-172 [Conf]
  10. John M. Emmert, Dinesh Bhatia
    Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:141-150 [Conf]
  11. John M. Emmert, Dinesh Bhatia
    Tabu Search: Ultra-Fast Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:81-90 [Conf]
  12. John M. Emmert, Akash Randhar, Dinesh Bhatia
    Fast Floorplanning for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:129-138 [Conf]
  13. PariVallal Kannan, Dinesh Bhatia
    Tightly Integrated Placement and Routing for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:233-242 [Conf]
  14. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:37-47 [Conf]
  15. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    Rapid and Reliable Routability Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:242-252 [Conf]
  16. Doug Smith, Dinesh Bhatia
    RACE: Reconfigurable and Adaptive Computing Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:87-95 [Conf]
  17. Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara
    FPGA Architecture for Standby Power Management. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:181-188 [Conf]
  18. Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
    Pseudoexhaustive BIST for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:523-527 [Conf]
  19. PariVallal Kannan, Dinesh Bhatia
    Interconnect Estimation for FPGAs under Timing Driven Domains. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:344-349 [Conf]
  20. Vijayanand Sankarasubramanian, Dinesh Bhatia
    Multiway Partitioner for High Performance FPGA Based Board Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:579-0 [Conf]
  21. Gregory Tumbush, Dinesh Bhatia
    Partitioning Under Timing and Area Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:614-620 [Conf]
  22. Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon
    Efficient Reconfiguration of WSI Arrays. [Citation Graph (0, 0)][DBLP]
    ICSI, 1990, pp:47-56 [Conf]
  23. Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara
    Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  24. John M. Emmert, Dinesh Bhatia
    Fast timing driven placement using tabu search. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:302-305 [Conf]
  25. Gregory Tumbush, Dinesh Bhatia
    Clustering to improve bi-partition quality and run time. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:145-148 [Conf]
  26. Karthikeya M. Gajjala Purna, Dinesh Bhatia
    Emulating Large Designs on Small Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:58-63 [Conf]
  27. Shankar Balachandran, Dinesh Bhatia
    A-priori wirelength and interconnect estimation based on circuit characteristics. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:77-84 [Conf]
  28. Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
    On Routing Demand and Congestion Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:639-646 [Conf]
  29. Dinesh Bhatia
    Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:356-359 [Conf]
  30. Dinesh Bhatia, James Haralambides
    Resource requirements for field programmable interconnection chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:376-380 [Conf]
  31. Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori
    Hierarchical Reconfiguration of VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:349-352 [Conf]
  32. Raghu Burra, Dinesh Bhatia
    Timing Driven Multi-FPGA Board Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:234-0 [Conf]
  33. Amit Chowdhary, Dinesh Bhatia
    Detailed Routing of Multi-Terminal Nets in FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:237-242 [Conf]
  34. PariVallal Kannan, Dinesh Bhatia
    Estimating Pre-Placement FPGA Interconnection Requirements. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:869-0 [Conf]
  35. Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
    Exploring Logic Block Granularity in Leakage Tolerant FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:754-757 [Conf]
  36. Jianzhong Shi, Akash Randhar, Dinesh Bhatia
    Macro Block Based FPGA Floorplanning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:21-26 [Conf]
  37. Natesan Venkateswaran, Dinesh Bhatia
    Clock-Skew Constrained Cell Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:146-149 [Conf]
  38. Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon, Carolyn Haibt Norton
    Improved Algorithms for Routing on Two-Dimensional Grids. [Citation Graph (0, 0)][DBLP]
    WG, 1992, pp:114-122 [Conf]
  39. John M. Emmert, Sandeep Lodha, Dinesh Bhatia
    On Using Tabu Search for Design Automation of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    J. Heuristics, 2003, v:9, n:1, pp:75-90 [Journal]
  40. Dinesh Bhatia, James Haralambides
    Bounds, designs and layouts for multi-terminal FPIC architectures. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:28, n:2, pp:141-156 [Journal]
  41. Karthikeya M. Gajjala Purna, Dinesh Bhatia
    Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:6, pp:579-590 [Journal]
  42. Shankar Balachandran, Dinesh Bhatia
    A priori wirelength and interconnect estimation based on circuit characteristic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1054-1065 [Journal]
  43. Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
    Pseudo-exhaustive built-in TPG for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1160-1171 [Journal]
  44. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    On metrics for comparing interconnect estimation methods for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:381-385 [Journal]
  45. Manjunath Gangadhar, Dinesh Bhatia
    FPGA based EBCOT architecture for JPEG 2000. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:363-373 [Journal]
  46. Shilpa Bhoj, Dinesh Bhatia
    Thermal Modeling and Temperature Driven Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1053-1056 [Conf]
  47. Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara
    Generic Network Interfaces for Plug and Play NoC Based Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:287-298 [Conf]
  48. Dinesh Bhatia, James Haralambides
    Resource requirements and layouts for field programmable interconnection chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:346-355 [Journal]
  49. Abhiman Hande, Todd Polk, William Walker, Dinesh Bhatia
    Indoor solar energy harvesting for sensor network router nodes. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:6, pp:420-432 [Journal]

  50. Pre-route Interconnect Capacitance and Power Estimation in FPGAs. [Citation Graph (, )][DBLP]


  51. A dynamic temperature control simulation system for FPGAs. [Citation Graph (, )][DBLP]


  52. Early stage FPGA interconnect leakage power estimation. [Citation Graph (, )][DBLP]


  53. Power efficient multi-band contextual activity monitoring for assistive environments. [Citation Graph (, )][DBLP]


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