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Chunhong Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chunhong Chen
    Probabilistic Analysis of Rectilinear Steiner Trees. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:484-488 [Conf]
  2. Chunhong Chen, Majid Sarrafzadeh
    Power reduction by simultaneous voltage scaling and gate sizing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:333-338 [Conf]
  3. Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication in technology independent phase. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:577-582 [Conf]
  4. Chunhong Chen, Majid Sarrafzadeh
    Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1016-1020 [Conf]
  5. Chunhong Chen, Majid Sarrafzadeh
    Provably good algorithm for low power consumption with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:76-79 [Conf]
  6. Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Potential Slack: An Effective Metric of Combinational Circuit Performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:198-201 [Conf]
  7. Chunhong Chen, Majid Sarrafzadeh
    An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:222-0 [Conf]
  8. Chunhong Chen, Jiang Zhao, Majid Ahmadi
    A semi-Gray encoding algorithm for low-power state assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:389-392 [Conf]
  9. Chunhong Chen, Changjun Kang, Majid Sarrafzadeh
    Activity-sensitive clock tree construction for low power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:279-282 [Conf]
  10. Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min
    Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:357-362 [Conf]
  11. Chunhong Chen
    Physical design with multiple on-chip voltages. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:118-118 [Conf]
  12. Jialin Mi, Chunhong Chen
    Finite State Machine Implementation with Single-Electron Tunneling Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:237-241 [Conf]
  13. Jialin Mi, Chunhong Chen
    Power-Oriented Delay Budgeting for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:361-366 [Conf]
  14. Chunhong Chen
    Probabilistic Analysis of Rectilinear Steiner Trees. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:484-488 [Conf]
  15. Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
    Budget Management with Applications. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 2002, v:34, n:3, pp:261-275 [Journal]
  16. Chunhong Chen, Jiang Zhao, Majid Ahmadi
    A Novel State Encoding Algorithm for Low Power Implementation. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:3, pp:597-604 [Journal]
  17. Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Predicting potential performance for digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:253-262 [Journal]
  18. Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
    Activity-driven clock design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:705-714 [Journal]
  19. Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:42-51 [Journal]
  20. Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu
    Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2124-2127 [Conf]
  21. Jialin Mi, Chunhong Chen, H. K. Kwan
    Power-oriented delay budgeting for combinational circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  22. Yanjie Mao, Chunhong Chen
    Performance Evaluation and Optimization of Full Adders with Single-Electron Technology. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:2136-2139 [Conf]
  23. Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh
    On gate level power optimization using dual-supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:616-629 [Journal]
  24. Chunhong Chen, Jiang Zhao, M. Ahmadi
    Probability-based approach to rectilinear Steiner tree problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:836-843 [Journal]

  25. An experimental study on multi-island structures for single-electron tunneling based threshold logic. [Citation Graph (, )][DBLP]


  26. Protocol-level performance analysis for anti-collision protocols in RFID systems. [Citation Graph (, )][DBLP]


  27. Power-management-based Chien search for low power BCH decoder. [Citation Graph (, )][DBLP]


  28. Parameter optimization for growth model of greenhouse crop using genetic algorithms. [Citation Graph (, )][DBLP]


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