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Publications of Author

1. Sanjukta Bhanja, N. Ranganathan
   Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:187-192 [Conf]
   
2. Sanjukta Bhanja, N. Ranganathan
   Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:209-214 [Conf]
   
3. Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
   Novel designs for thermally robust coplanar crossing in QCA. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:786-791 [Conf]
   
4. Sanjukta Bhanja, Lynn M. Fletcher-Heath, Lawrence O. Hall, Dmitry B. Goldgof, Jeffrey P. Krischer
   A Qualitative Expert System for Clinical Trial Assignment. [Citation Graph (0, 0)][DBLP]
   FLAIRS Conference, 1998, pp:84-88 [Conf]
   
5. Nirmal Ramalingam, Sanjukta Bhanja
   Causal probabilistic input dependency learning for switching model in VLSI circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:112-115 [Conf]
   
6. Karthikeyan Lingasubramanian, Sanjukta Bhanja
   Probabilistic maximum error modeling for unreliable logic circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:223-226 [Conf]
   
7. Sanjukta Bhanja, N. Ranganathan
   Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. [Citation Graph (0, 0)][DBLP]
   ICCD, 2002, pp:388-390 [Conf]
   
8. Shiva Shankar Ramani, Sanjukta Bhanja
   Any-time probabilistic switching model using bayesian networks. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:86-89 [Conf]
   
9. Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
   Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:586-591 [Conf]
   
10. Sanjukta Bhanja, N. Ranganathan
    Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:187-192 [Conf]
    
11. Thara Rejimon, Sanjukta Bhanja
    An Accurate Probalistic Model for Error Detection. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:717-722 [Conf]
    
12. Thara Rejimon, Sanjukta Bhanja
    Wide Limited Switch Dynamic Logic Circuit Implementations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:94-99 [Conf]
    
13. Saket Srivastava, Sanjukta Bhanja
    Hierarchical Probabilistic Macromodeling for QCA Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:2, pp:174-190 [Journal]
    
14. Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
    A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:773-796 [Journal]
    
15. Sanjukta Bhanja, N. Ranganathan
    Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1360-1370 [Journal]
    
16. Thara Rejimon, Sanjukta Bhanja
    A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1130-1139 [Journal]
    
17. Sanjukta Bhanja, N. Ranganathan
    Switching activity estimation of VLSI circuits using Bayesian networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:558-567 [Journal]
    
18. Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
    QCA Circuits for Robust Coplanar Crossing. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:193-210 [Journal]
    
19. 
    Defect characterization in magnetic field coupled arrays. [Citation Graph (, )][DBLP]
    
    
20. 
    An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. [Citation Graph (, )][DBLP]
    
    
21. 
    Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis [Citation Graph (, )][DBLP]