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Vincent John Mooney III: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Arunkumar Balasundaram, Angelo Pereira, Jun-Cheol Park, Vincent John Mooney III
    Golay and wavelet error control codes in VLSI. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:563-564 [Conf]
  2. Jaehwan John Lee, Vincent John Mooney III
    A novel O(n) parallel banker's algorithm for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1304-1308 [Conf]
  3. Bilge Saglam Akgul, Jaehwan Lee, Vincent John Mooney III
    A system-on-a-chip lock cache with task preemption support. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:149-157 [Conf]
  4. Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John Mooney III, Krishna V. Palem, Kiran Puttaswamy, Weng-Fai Wong
    The emerging power crisis in embedded processors: what can a poor compiler do? [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:176-180 [Conf]
  5. Mohamed Shalan, Vincent John Mooney III
    A dynamic memory management unit for embedded real-time system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:180-186 [Conf]
  6. Claudionor José Nunes Coelho Jr., Jerry Chih-Yuan Yang, Vincent John Mooney III, Giovanni De Micheli
    Redesigning hardware-software systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:116-123 [Conf]
  7. Jaehwan Lee, Vincent John Mooney III
    A novel deadlock avoidance algorithm and its hardware implementation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:200-205 [Conf]
  8. Mohamed Shalan, Vincent John Mooney III
    Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:79-84 [Conf]
  9. Pun H. Shiu, Yudong Tan, Vincent John Mooney III
    A novel parallel deadlock detection algorithm and architecture. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:73-78 [Conf]
  10. Bilge Saglam Akgul, Vincent John Mooney III
    System-on-a-chip processor synchronization support in hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:633-641 [Conf]
  11. Bilge Saglam Akgul, Vincent John Mooney III
    PARLAK: Parametrized Lock Cache Generator. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11138-11139 [Conf]
  12. Yudong Tan, Vincent John Mooney III
    Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1034-1039 [Conf]
  13. Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III
    A Comparison of Five Different Multiprocessor SoC Bus Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:202-211 [Conf]
  14. Tankut Akgul, Pramote Kuacharoen, Vincent John Mooney III, Vijay K. Madisetti
    A Debugger RTOS for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2001, pp:264-0 [Conf]
  15. Ozgur Celebican, Tajana Simunic Rosing, Vincent John Mooney III
    Energy estimation of peripheral devices in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:430-435 [Conf]
  16. Vincent John Mooney III, Giovanni De Micheli
    Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:605-612 [Conf]
  17. Tankut Akgul, Vincent John Mooney III, Santosh Pande
    A Fast Assembly Level Reverse Execution Method via Dynamic Slicing. [Citation Graph (0, 0)][DBLP]
    ICSE, 2004, pp:522-531 [Conf]
  18. Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy
    System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:225-230 [Conf]
  19. Vincent John Mooney III
    Path-based Edge Activation for Dynamic Run-Time Scheduling. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:30-37 [Conf]
  20. Vincent John Mooney III, George F. Riley, Eung S. Shin
    Round-Robin Arbiter Design and Generation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:243-248 [Conf]
  21. Yudong Tan, Vincent John Mooney III
    WCRT analysis for a uniprocessor with a unified prioritized cache. [Citation Graph (0, 0)][DBLP]
    LCTES, 2005, pp:175-182 [Conf]
  22. Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger
    Sleepy Stack Reduction of Leakage Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:148-158 [Conf]
  23. Vincent John Mooney III, Douglas M. Blough
    A Hardware-Software Real-Time Operating System Framework for SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:44-51 [Journal]
  24. Kyeong Keol Ryu, Vincent John Mooney III
    Automated bus generation for multiprocessor SoC design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1531-1549 [Journal]
  25. Yudong Tan, Vincent John Mooney III
    Timing analysis for preemptive multitasking real-time systems with caches. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:1, pp:- [Journal]
  26. Jaehwan John Lee, Vincent John Mooney III
    An o(min(m, n)) parallel deadlock detection algorithm. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:573-586 [Journal]
  27. Tankut Akgul, Vincent John Mooney III
    Assembly instruction level reverse execution for debugging. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Softw. Eng. Methodol., 2004, v:13, n:2, pp:149-198 [Journal]
  28. Jun-Cheol Park, Vincent John Mooney III
    Pareto Points in SRAM Design Using the Sleepy Stack Approach. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:163-177 [Conf]
  29. Jun-Cheol Park, Vincent John Mooney III
    Sleepy Stack Leakage Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1250-1263 [Journal]
  30. Jun-Cheol Park, Vincent John Mooney III, Sudarshan K. Srinivasan
    Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1019-1024 [Journal]

  31. A More Precise Model of Noise Based PCMOS Errors. [Citation Graph (, )][DBLP]


  32. Task Scheduling for Control Oriented Requirements for Cyber-Physical Systems. [Citation Graph (, )][DBLP]


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