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Andrew A. Kennings: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
    Function Smoothing with Applications to VLSI Layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:225-0 [Conf]
  2. Andrew A. Kennings, Igor L. Markov
    Analytical minimization of half-perimeter wirelength. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:179-184 [Conf]
  3. Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
    Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:349-354 [Conf]
  4. Austin Hung, William D. Bishop, Andrew A. Kennings
    Symmetric Multiprocessing on Programmable Chips Made Easy. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:240-245 [Conf]
  5. Kristofer Vorwerk, Andrew A. Kennings
    An Improved Multi-Level Framework for Force-Directed Placement. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:902-907 [Conf]
  6. Austin Hung, William D. Bishop, Andrew A. Kennings
    Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:312- [Conf]
  7. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings
    Board-level multiterminal net assignment. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:130-135 [Conf]
  8. Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat
    Floorplan repair using dynamic whitespace management. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:552-557 [Conf]
  9. Kristofer Vorwerk, Andrew A. Kennings
    Mixed-size placement via line search. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:899-904 [Conf]
  10. Kristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli
    Engineering details of a stable force-directed placer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:573-580 [Conf]
  11. William N. N. Hung, Xiaoyu Song, Alan J. Coppola, Andrew A. Kennings
    On segmented channel routability. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:169-172 [Conf]
  12. Andrew A. Kennings, Kristofer Vorwerk
    Force-Directed Methods for Generic Placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2076-2087 [Journal]
  13. William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Andrew A. Kennings, Alan J. Coppola
    Segmented channel routability via satisfiability. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:4, pp:517-528 [Journal]
  14. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola
    Board-level multiterminal net assignment for the partial cross-bar architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:511-514 [Journal]

  15. FPGA technology mapping with encoded libraries andstaged priority cuts. [Citation Graph (, )][DBLP]


  16. Improving Annealing Via Directed Moves. [Citation Graph (, )][DBLP]


  17. Improving Timing-Driven FPGA Packing With Physical Information. [Citation Graph (, )][DBLP]


  18. A technique for minimizing power during FPGA placement. [Citation Graph (, )][DBLP]


  19. Physical optimization for FPGAs using post-placement topology rewriting. [Citation Graph (, )][DBLP]


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