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Yirng-An Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jiunn-Chern Chen, Yirng-An Chen
    Equivalence checking of integer multipliers. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:169-174 [Conf]
  2. Bwolen Yang, Yirng-An Chen, Randal E. Bryant, David R. O'Hallaron
    Space- and Time-Efficient BDD Construction via Working Set Control. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:423-432 [Conf]
  3. Yirng-An Chen, Randal E. Bryant
    Verification of Floating-Point Adders. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:488-499 [Conf]
  4. Randal E. Bryant, Yirng-An Chen
    Verification of Arithmetic Circuits with Binary Moment Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:535-541 [Conf]
  5. Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai
    Advanced techniques for RTL debugging. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:362-367 [Conf]
  6. Yirng-An Chen, Edmund M. Clarke, Pei-Hsin Ho, Yatin Vasant Hoskote, Timothy Kam, Manpreet Khaira, John W. O'Leary, Xudong Zhao
    Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:19-33 [Conf]
  7. Yirng-An Chen, Randal E. Bryant
    ACV: an arithmetic circuit verifier. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:361-365 [Conf]
  8. Yirng-An Chen, Randal E. Bryant
    PHDD: an efficient graph representation for floating point circuit verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:2-7 [Conf]
  9. Randal E. Bryant, Yirng-An Chen
    Verification of arithmetic circuits using binary moment diagrams. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:2, pp:137-155 [Journal]
  10. Yirng-An Chen, Youn-Long Lin, Long-Wen Chang
    A Systolic Algorithm for the k-Nearest Neighbors Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:1, pp:103-108 [Journal]
  11. Yirng-An Chen, Randal E. Bryant
    An efficient graph representation for arithmetic circuitverification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1443-1454 [Journal]

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