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Sudarshan Banerjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt
    PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:491-496 [Conf]
  2. Sudarshan Banerjee, Nikil D. Dutt
    Efficient search space exploration for HW-SW partitioning. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:122-127 [Conf]
  3. Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian
    Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:16-21 [Conf]
  4. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
    Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:335-340 [Conf]
  5. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1246-1251 [Conf]
  6. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
    Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:273-274 [Conf]
  7. Sudarshan Banerjee, Nikil D. Dutt
    FIFO power optimization for on-chip networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:187-191 [Conf]
  8. John Augustine, Sudarshan Banerjee, Sandy Irani
    Strip packing with precedence constraints and strip packing with release times. [Citation Graph (0, 0)][DBLP]
    SPAA, 2006, pp:180-189 [Conf]
  9. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
    Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:651-656 [Conf]
  10. Sudarshan Banerjee, Sanjeev Saxena
    Parallel Algorithms for Finding the Most Vital Edge in Weighted Graphs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:46, n:1, pp:101-104 [Journal]
  11. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:754-762 [Journal]
  12. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera
    Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:771-776 [Conf]
  13. Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  14. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
    Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1189-1202 [Journal]

  15. Energy-aware co-processor selection for embedded processors on FPGAs. [Citation Graph (, )][DBLP]


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