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Nikil Dutt: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt
    PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:491-496 [Conf]
  2. Hyunok Oh, Nikil Dutt, Soonhoi Ha
    Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:497-502 [Conf]
  3. Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
    Automated throughput-driven synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:495-498 [Conf]
  4. Aviral Shrivastava, Ilya Issenin, Nikil Dutt
    Compilation techniques for energy reduction in horizontally partitioned cache architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:90-96 [Conf]
  5. Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian
    Mitigating soft error failures for multimedia applications by selective data protection. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:411-420 [Conf]
  6. Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian
    Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:16-21 [Conf]
  7. Ilya Issenin, Nikil Dutt
    Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:294-299 [Conf]
  8. Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt
    Introduction of local memory elements in instruction set extensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:729-734 [Conf]
  9. Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt
    Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:49-52 [Conf]
  10. Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta
    Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:556-561 [Conf]
  11. Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta
    Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:474-479 [Conf]
  12. Ann Gordon-Ross, Frank Vahid, Nikil Dutt
    Automatic Tuning of Two-Level Caches to Embedded Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:208-213 [Conf]
  13. Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau
    Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:114-121 [Conf]
  14. Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt
    Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:202-207 [Conf]
  15. Prabhat Mishra, Nikil Dutt
    Graph-Based Functional Test Program Generation for Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:182-187 [Conf]
  16. Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek
    Automatic generation of operation tables for fast exploration of bypasses in embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1197-1202 [Conf]
  17. Gabor Madl, Sudeep Pasricha, Luis Angel D. Bathen, Nikil Dutt, Qiang Zhu
    Formal performance evaluation of AMBA-based system-on-chip designs. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:311-320 [Conf]
  18. Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta
    Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:33-38 [Conf]
  19. Ann Gordon-Ross, Frank Vahid, Nikil Dutt
    A first look at the interplay of code reordering and configurable caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:416-421 [Conf]
  20. Jong-eun Lee, Kiyoung Choi, Nikil Dutt
    Efficient instruction encoding for automatic instruction set design of configurable ASIPs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:649-654 [Conf]
  21. Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil Dutt
    Low power address encoding using self-organizing lists. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:188-193 [Conf]
  22. Radu Cornea, Alex Nicolau, Nikil Dutt
    Video Stream Annotations for Energy Trade-offs in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ISPDC, 2006, pp:17-23 [Conf]
  23. David J. Kolson, Alexandru Nicolau, Nikil Dutt, Ken Kennedy
    Optimal register assignment to loops for embedded code generation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:42-47 [Conf]
  24. Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu
    A comprehensive estimation technique for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:122-127 [Conf]
  25. Prabhat Mishra, Arun Kejariwal, Nikil Dutt
    Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:226-232 [Conf]
  26. Gabor Madl, Nikil Dutt
    Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:59-68 [Conf]
  27. Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt
    Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:97-102 [Conf]
  28. Prabhat Mishra, Arun Kejariwal, Nikil Dutt
    Synthesis-driven Exploration of Pipelined Embedded Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:921-926 [Conf]
  29. Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
    Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:8- [Conf]
  30. Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir
    A Top-Down Methodology for Microprocessor Validation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:122-131 [Journal]
  31. Minyoung Kim, Hyunok Oh, Nikil Dutt, Alex Nicolau, Nalini Venkatasubramanian
    PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh. [Citation Graph (0, 0)][DBLP]
    Mobile Computing and Communications Review, 2006, v:10, n:3, pp:58-69 [Journal]
  32. Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra
    A retargetable framework for instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:431-452 [Journal]
  33. Prabhat Mishra, Nikil Dutt
    Modeling and validation of pipeline specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:114-139 [Journal]
  34. Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt
    Processor-memory coexploration using an architecture description language. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:140-162 [Journal]
  35. Prabhat Mishra, Aviral Shrivastava, Nikil Dutt
    Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:626-658 [Journal]
  36. Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek
    Software controlled memory layout reorganization for irregular array access patterns. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:179-188 [Conf]
  37. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera
    Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:771-776 [Conf]
  38. Qiang Zhu, Aviral Shrivastava, Nikil Dutt
    Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1164-1169 [Conf]
  39. Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian
    Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters. [Citation Graph (0, 0)][DBLP]
    FORMATS, 2007, pp:257-273 [Conf]
  40. Radu Cornea, Alex Nicolau, Nikil Dutt
    Annotation Integration and Trade-off Analysis for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  41. Nikil Dutt
    Modeling of Software-Hardware Complexes. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:423-425 [Conf]
  42. Ilya Issenin, Nikil Dutt
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:299-312 [Conf]
  43. Ilya Issenin, Nikil Dutt
    FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  44. Mehrdad Reshadi, Nikil Dutt
    Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  45. Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  46. Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt
    DRDU: A data reuse analysis technique for efficient scratch-pad memory management. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  47. Nikil Dutt
    Editorial. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]

  48. Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. [Citation Graph (, )][DBLP]

  49. Quo vadis, BTSoC (Billion Transistor SoC)? [Citation Graph (, )][DBLP]

  50. A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. [Citation Graph (, )][DBLP]

  51. ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. [Citation Graph (, )][DBLP]

  52. Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. [Citation Graph (, )][DBLP]

  53. Methodology for multi-granularity embedded processor power model generation for an ESL design flow. [Citation Graph (, )][DBLP]

  54. ESL hand-off: fact or EDA fiction? [Citation Graph (, )][DBLP]

  55. Constraint Refinement for Online Verifiable Cross-Layer System Adaptation. [Citation Graph (, )][DBLP]

  56. Memory-aware NoC Exploration and Design. [Citation Graph (, )][DBLP]

  57. TRAM: A tool for Temperature and Reliability Aware Memory Design. [Citation Graph (, )][DBLP]

  58. Performance estimation of distributed real-time embedded systems by discrete event simulations. [Citation Graph (, )][DBLP]

  59. Cross-layer co-exploration of exploiting error resilience for video over wireless applications. [Citation Graph (, )][DBLP]

  60. Annotation Based Multimedia Streaming Over Wireless Networks. [Citation Graph (, )][DBLP]

  61. RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. [Citation Graph (, )][DBLP]

  62. System level power estimation methodology with H.264 decoder prediction IP case study. [Citation Graph (, )][DBLP]

  63. An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices. [Citation Graph (, )][DBLP]

  64. Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. [Citation Graph (, )][DBLP]

  65. Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems. [Citation Graph (, )][DBLP]

  66. Compiler driven data layout optimization for regular/irregular array access patterns. [Citation Graph (, )][DBLP]

  67. Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach. [Citation Graph (, )][DBLP]

  68. Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. [Citation Graph (, )][DBLP]

  69. A Conservative Approximation Method for the Verification of Preemptive Scheduling Using Timed Automata. [Citation Graph (, )][DBLP]

  70. Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. [Citation Graph (, )][DBLP]

  71. Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. [Citation Graph (, )][DBLP]

  72. Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. [Citation Graph (, )][DBLP]

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