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Publications of Author

1. Deming Chen, Jason Cong
   Register binding and port assignment for multiplexer optimization. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:68-73 [Conf]
   
2. Deming Chen, Jason Cong, Junjuan Xu
   Optimal module and voltage assignment for low-power. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:850-855 [Conf]
   
3. Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
   Optimality study of resource binding with multi-Vdds. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:580-585 [Conf]
   
4. Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong
   A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:117-120 [Conf]
   
5. Joey Y. Lin, Deming Chen, Jason Cong
   Optimal simultaneous mapping and clustering for FPGA delay optimization. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:472-477 [Conf]
   
6. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
   Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
   FPGA, 2001, pp:39-47 [Conf]
   
7. Deming Chen, Jason Cong, Fei Li, Lei He
   Low-power technology mapping for FPGA architectures with dual supply voltages. [Citation Graph (0, 0)][DBLP]
   FPGA, 2004, pp:109-117 [Conf]
   
8. Fei Li, Deming Chen, Lei He, Jason Cong
   Architecture evaluation for power-efficient FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 2003, pp:175-184 [Conf]
   
9. Deming Chen, Jason Cong
   DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:752-759 [Conf]
   
10. Deming Chen, Jason Cong
    Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:70-73 [Conf]
    
11. Deming Chen, Jason Cong, Yiping Fan
    Low-power high-level synthesis for FPGA architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:134-139 [Conf]
    
12. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
    Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1424-1431 [Journal]
    
13. Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong
    Power modeling and characteristics of field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1712-1724 [Journal]
    
14. Deming Chen, Jason Cong, Junjuan Xu
    Optimal simultaneous module and multivoltage assignment for low power. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:362-386 [Journal]
    
15. Lei Cheng, Deming Chen, Martin D. F. Wong
    DDBDD: Delay-Driven BDD Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:910-915 [Conf]
    
16. Lei Cheng, Deming Chen, Martin D. F. Wong
    GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:318-323 [Conf]
    
17. 
    FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization. [Citation Graph (, )][DBLP]
    
    
18. 
    High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. [Citation Graph (, )][DBLP]
    
    
19. 
    VEBoC: Variation and error-aware design for billions of devices on a chip. [Citation Graph (, )][DBLP]
    
    
20. 
    FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. [Citation Graph (, )][DBLP]
    
    
21. 
    Clock tree synthesis under aggressive buffer insertion. [Citation Graph (, )][DBLP]
    
    
22. 
    Reconfigurable circuit design with nanomaterials. [Citation Graph (, )][DBLP]
    
    
23. 
    Efficient ASIP design for configurable processors with fine-grained resource sharing. [Citation Graph (, )][DBLP]
    
    
24. 
    FPCNA: a field programmable carbon nanotube array. [Citation Graph (, )][DBLP]
    
    
25. 
    Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. [Citation Graph (, )][DBLP]
    
    
26. 
    CMOS vs Nano: comrades or rivals? [Citation Graph (, )][DBLP]
    
    
27. 
    Blueshift: Designing processors for timing speculation from the ground up. [Citation Graph (, )][DBLP]
    
    
28. 
    Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. [Citation Graph (, )][DBLP]
    
    
29. 
    Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. [Citation Graph (, )][DBLP]
    
    
30. 
    DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior. [Citation Graph (, )][DBLP]
    
    
31. 
    High-performance CUDA kernel execution on FPGAs. [Citation Graph (, )][DBLP]
    
    
32. 
    A routing approach to reduce glitches in low power FPGAs. [Citation Graph (, )][DBLP]
    
    
33. 
    Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. [Citation Graph (, )][DBLP]
    
    
34. 
    Workload adaptive shared memory multicore processors with reconfigurable interconnects. [Citation Graph (, )][DBLP]
    
    
35. 
    FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. [Citation Graph (, )][DBLP]