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Jason Cong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Deming Chen, Jason Cong
    Register binding and port assignment for multiplexer optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:68-73 [Conf]
  2. Deming Chen, Jason Cong, Junjuan Xu
    Optimal module and voltage assignment for low-power. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:850-855 [Conf]
  3. Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng
    Bitwidth-aware scheduling and binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:856-861 [Conf]
  4. Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
    An automated design flow for 3D microarchitecture evaluation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:384-389 [Conf]
  5. Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu
    Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:277-282 [Conf]
  6. Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong
    Relaxed Simulated Tempering for VLSI Floorplan Designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:13-16 [Conf]
  7. Jason Cong, Sung Kyu Lim
    Edge separability based circuit clustering with application to circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:429-434 [Conf]
  8. Jason Cong, Sung Kyu Lim
    Performance driven multiway partitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:441-446 [Conf]
  9. Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe
    Are we ready for system-level synthesis? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  10. Jason Cong, David Zhigang Pan
    Interconnect Delay Estimation Models for Synthesis and Design Planning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:97-100 [Conf]
  11. Jason Cong, David Zhigang Pan, Prasanna V. Srinivas
    Improved crosstalk modeling for noise constrained interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:373-378 [Conf]
  12. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Fast floorplanning by look-ahead enabled recursive bipartitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1119-1122 [Conf]
  13. Jason Cong, Songjie Xu
    Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:157-162 [Conf]
  14. Jason Cong, Min Xie
    A robust detailed placement for mixed-size IC designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:188-194 [Conf]
  15. Jason Cong, Dongmin Xu
    Exploitation signal flow and logic dependency in standard cell placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  16. Jason Cong, Yan Zhang
    Thermal-driven multilevel routing for 3-D ICs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:121-126 [Conf]
  17. Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
    Microarchitecture evaluation with floorplanning and interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:8-15 [Conf]
  18. Maogang Wang, Sung Lim, Jason Cong, Majid Sarrafzadeh
    Multi-way partitioning using bi-partition heuristics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:667- [Conf]
  19. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
    Architecture and synthesis for multi-cycle on-chip communication. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:77-78 [Conf]
  20. Chin-Chih Chang, Jason Cong
    An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:600-603 [Conf]
  21. Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
    Optimality study of resource binding with multi-Vdds. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:580-585 [Conf]
  22. Jason Cong, Yuzheng Ding
    On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:213-218 [Conf]
  23. Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
    Behavior and communication co-optimization for systems with sequential communication media. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:675-678 [Conf]
  24. Jason Cong, Yiping Fan, Zhiru Zhang
    Architecture-level synthesis for automatic interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:602-607 [Conf]
  25. Jason Cong, Hui Huang
    Depth optimal incremental mapping for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:290-293 [Conf]
  26. Jason Cong, Yean-Yow Hwang
    Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:726-729 [Conf]
  27. Jason Cong, Lars W. Hagen, Andrew B. Kahng
    Net Partitions Yield Better Module Partitions. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:47-52 [Conf]
  28. Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen
    Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:627-632 [Conf]
  29. Jason Cong, Yean-Yow Hwang, Songjie Xu
    Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:373-378 [Conf]
  30. Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
    Microarchitecture evaluation with physical planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:32-35 [Conf]
  31. Jason Cong, Zheng Li, Rajive Bagrodia
    Acyclic Multi-Way Partitioning of Boolean Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:670-675 [Conf]
  32. Jason Cong, Sung Kyu Lim, Chang Wu
    Performance driven multi-level and multiway partitioning with retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:274-279 [Conf]
  33. Jason Cong, Honching Li, Chang Wu
    Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:460-465 [Conf]
  34. Jason Cong, Kwok-Shing Leung, Dian Zhou
    Performance-Driven Interconnect Design Based on Distributed RC Delay Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:606-611 [Conf]
  35. Jason Cong, Patrick H. Madden
    Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:356-361 [Conf]
  36. Jason Cong, David Zhigang Pan
    Interconnect Estimation and Dlanning for Deep Submicron Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:507-510 [Conf]
  37. Jason Cong, Bryan Preas, C. L. Liu
    General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:709-715 [Conf]
  38. Jason Cong, Michail Romesis
    Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:389-394 [Conf]
  39. Jason Cong, M'Lissa Smith
    A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:755-760 [Conf]
  40. Jason Cong, Chang Wu
    FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:644-649 [Conf]
  41. Jason Cong, Chang Wu
    Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:330-335 [Conf]
  42. Jason Cong, Songjie Xu
    Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:704-707 [Conf]
  43. Jason Cong, Xin Yuan
    Routing tree construction under fixed buffer locations. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:379-384 [Conf]
  44. Jason Cong, Xin Yuan
    Multilevel global placement with retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:208-213 [Conf]
  45. Jason Cong, Zhiru Zhang
    An efficient and versatile scheduling algorithm based on SDC formulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:433-438 [Conf]
  46. Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar
    What happened to ASIC?: Go (recon)figure? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:185- [Conf]
  47. Andrew B. Kahng, Jason Cong, Gabriel Robins
    High-Performance Clock Routing Based on Recursive Geometric Aatching. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:322-327 [Conf]
  48. Kei-Yong Khoo, Jason Cong
    An Efficient Multilayer MCM Router Based on Four-Via Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:590-595 [Conf]
  49. Joey Y. Lin, Deming Chen, Jason Cong
    Optimal simultaneous mapping and clustering for FPGA delay optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:472-477 [Conf]
  50. Khe-Sing The, D. F. Wong, Jason Cong
    VIA Minimization by Layout Modification. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:799-802 [Conf]
  51. Taku Uchino, Jason Cong
    An Interconnect Energy Model Considering Coupling Effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:555-558 [Conf]
  52. Jason Cong, John Peck
    On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:246-248 [Conf]
  53. Jason Cong, Yuzheng Ding
    On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:82-88 [Conf]
  54. Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
    Instruction set extension with shadow registers for configurable processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:99-106 [Conf]
  55. Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
    Application-specific instruction generation for configurable processor architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:183-189 [Conf]
  56. Jason Cong, Yean-Yow Hwang
    Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:68-74 [Conf]
  57. Jason Cong, Yean-Yow Hwang
    Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:35-42 [Conf]
  58. Jason Cong, Yean-Yow Hwang
    Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:27-34 [Conf]
  59. Jason Cong, Hui Huang, Xin Yuan
    Technology mapping for k/m-macrocell based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:51-59 [Conf]
  60. Jason Cong, Yizhou Lin, Wangning Long
    SPFD-based global rewiring. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:77-84 [Conf]
  61. Jason Cong, Kirill Minkovich
    Optimality study of logic synthesis for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:33-40 [Conf]
  62. Jason Cong, John Peck, Yuzheng Ding
    RASP: A General Logic Synthesis System for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:137-143 [Conf]
  63. Jason Cong, Chang Wu, Yuzheng Ding
    Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:29-35 [Conf]
  64. Gang Chen, Jason Cong
    Simultaneous logic decomposition with technology mapping in FPGA designs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:48-55 [Conf]
  65. Gang Chen, Jason Cong
    Simultaneous timing-driven placement and duplication. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:51-59 [Conf]
  66. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
    Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:39-47 [Conf]
  67. Jason Cong, Songjie Xu
    Technology Mapping for FPGAs with Embedded Memory Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:179-188 [Conf]
  68. Jason Cong, Kenneth Yan
    Synthesis for FPGAs with embedded memory blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:75-82 [Conf]
  69. Deming Chen, Jason Cong, Fei Li, Lei He
    Low-power technology mapping for FPGA architectures with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:109-117 [Conf]
  70. Fei Li, Deming Chen, Lei He, Jason Cong
    Architecture evaluation for power-efficient FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:175-184 [Conf]
  71. Fei Li, Yan Lin, Lei He, Jason Cong
    Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:42-50 [Conf]
  72. Jason Cong, Kirill Minkovich
    Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:139-147 [Conf]
  73. Jason Cong, Guoling Han, Wei Jiang
    Synthesis of an application-specific soft multiprocessor system. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:99-107 [Conf]
  74. Gang Chen, Jason Cong
    Simultaneous Timing Driven Clustering and Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:158-167 [Conf]
  75. Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne Wolf
    How will CAD handle billion-transistor systems? (panel). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:5- [Conf]
  76. Deming Chen, Jason Cong
    DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:752-759 [Conf]
  77. Tony Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl
    Multilevel Optimization for Large-Scale Circuit Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:171-176 [Conf]
  78. Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze
    An Enhanced Multilevel Algorithm for Circuit Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:299-306 [Conf]
  79. Jason Cong, Yuzheng Ding
    An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:48-53 [Conf]
  80. Jason Cong, Yuzheng Ding
    Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:110-114 [Conf]
  81. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
    Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:536-543 [Conf]
  82. Jason Cong, Jie Fang, Kei-Yong Khoo
    An implicit connection graph maze routing algorithm for ECO routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:163-167 [Conf]
  83. Jason Cong, Jie Fang, Yan Zhang VI
    Multilevel Approach to Full-Chip Gridless Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:396-403 [Conf]
  84. Jason Cong, Lei He
    Optimal wiresizing for interconnects with multiple sources. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:568-574 [Conf]
  85. Jason Cong, Lei He
    An efficient approach to simultaneous transistor and interconnect sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:181-186 [Conf]
  86. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
    Global interconnect sizing and spacing with consideration of coupling capacitance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:628-633 [Conf]
  87. Jason Cong, Guoling Han, Zhiru Zhang
    Architecture and compilation for data bandwidth improvement in configurable embedded processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:263-270 [Conf]
  88. Jason Cong, Cheng-Kok Koh
    Simultaneous driver and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:206-212 [Conf]
  89. Jason Cong, Cheng-Kok Koh
    Interconnect layout optimization under higher-order RLC model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:713-720 [Conf]
  90. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing under Elmore delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:66-71 [Conf]
  91. Jason Cong, Tianming Kong, David Zhigang Pan
    Buffer block planning for interconnect-driven floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:358-363 [Conf]
  92. Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan
    Large-Scale Circuit Placement: Gap and Promise. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:883-890 [Conf]
  93. Jason Cong, Sung Kyu Lim
    Physical Planning with Retiming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:2-7 [Conf]
  94. Jason Cong, Kwok-Shing Leung
    Optimal wiresizing under the distributed Elmore delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:634-639 [Conf]
  95. Jason Cong, Sung Kyu Lim
    Multiway partitioning with pairwise movement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:512-516 [Conf]
  96. Jason Cong, Joey Y. Lin, Wangning Long
    A new enhanced SPFD rewiring algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:672-678 [Conf]
  97. Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu
    Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:441-446 [Conf]
  98. Jason Cong, Wilburt Labio, Narayanan Shivakumar
    Multi-way VLSI circuit partitioning based on dual net representation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:56-62 [Conf]
  99. Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
    Interconnect design for deep submicron ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:478-485 [Conf]
  100. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Robust mixed-size placement under tight white-space constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:165-172 [Conf]
  101. Jason Cong, Michail Romesis, Min Xie
    Optimality and Stability Study of Timing-Driven Placement Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:472-479 [Conf]
  102. Jason Cong, Jie Wei, Yan Zhang
    A thermal-driven floorplanning algorithm for 3D ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:306-313 [Conf]
  103. Jason Cong, Songjie Xu
    Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:40-44 [Conf]
  104. Jason Cong, Min Xie, Yan Zhang
    An enhanced multilevel routing system. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:51-58 [Conf]
  105. Jason Cong, Yan Zhang
    Thermal via planning for 3-D ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:745-752 [Conf]
  106. Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh
    Incremental CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:236-243 [Conf]
  107. Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong
    Intellectual property protection by watermarking combinational logic synthesis solutions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:194-198 [Conf]
  108. Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden
    Routability-driven placement and white space allocation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:394-401 [Conf]
  109. Takumi Okamoto, Jason Cong
    Buffered Steiner tree construction with wire sizing for interconnect layout optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:44-49 [Conf]
  110. Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong
    Gradual Relaxation Techniques with Applications to Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:529-535 [Conf]
  111. Jason Cong, Yiping Fan, Wei Jiang
    Platform-based resource binding using a distributed register-file microarchitecture. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:709-715 [Conf]
  112. Jason Cong, Chang Wu
    An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:572-578 [Conf]
  113. Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
    An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:154-158 [Conf]
  114. Jason Cong, Kei-Yong Khoo
    A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:319-322 [Conf]
  115. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong
    Performance-Driven Global Routing for Cell Based ICs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:170-173 [Conf]
  116. Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
    Minimum Density Interconneciton Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1865-1868 [Conf]
  117. Jason Cong, Cheng-Kok Koh
    Minimum-Cost Bounded-Skew Clock Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:215-218 [Conf]
  118. Jason Cong, Patrick H. Madden
    Performance Driven Routing with Mulitiple Sources. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:203-206 [Conf]
  119. Junjuan Xu, Jason Cong, Xu Cheng
    Lower-bound estimation for multi-bitwidth scheduling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:696-699 [Conf]
  120. Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong
    A Two-pole Circuit Model for VLSI High-speed Interconnection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2129-2132 [Conf]
  121. Deming Chen, Jason Cong
    Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:70-73 [Conf]
  122. Deming Chen, Jason Cong, Yiping Fan
    Low-power high-level synthesis for FPGA architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:134-139 [Conf]
  123. Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir
    Understanding the energy efficiency of SMT and CMP with multiclustering. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:48-53 [Conf]
  124. Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
    Simultaneous buffer and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:271-276 [Conf]
  125. Jason Cong, Patrick H. Madden
    Performance driven global routing for standard cell design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:73-80 [Conf]
  126. Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl
    An area-optimality study of floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:78-83 [Conf]
  127. Jason Cong, Michail Romesis, Min Xie
    Optimality, scalability and stability study of partitioning and placement algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:88-94 [Conf]
  128. Jason Cong, Majid Sarrafzadeh
    Incremental physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:84-92 [Conf]
  129. Jason Cong, Chang Wu
    Global clustering-based performance-driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:149-154 [Conf]
  130. Jason Cong, Jie Fang, Kei-Yong Khoo
    VIA design rule consideration in multi-layer maze routing algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:214-220 [Conf]
  131. Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
    Architecture and synthesis for multi-cycle communication. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:190-196 [Conf]
  132. Jason Cong, Lei He
    An efficient technique for device and interconnect optimization in deep submicron designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:45-51 [Conf]
  133. Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
    Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:88-95 [Conf]
  134. Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
    mPL6: a robust multilevel mixed-size placement engine. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:227-229 [Conf]
  135. Tony Chan, Jason Cong, Kenton Sze
    Multilevel generalized force-directed method for circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:185-192 [Conf]
  136. Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie
    mPL6: enhanced multilevel mixed-size placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:212-214 [Conf]
  137. Chin-Chih Chang, Jason Cong
    Pseudo pin assignment with crosstalk noise control. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:41-47 [Conf]
  138. Chin-Chih Chang, Jason Cong, David Zhigang Pan
    Physical hierarchy generation with routing congestion control. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:36-41 [Conf]
  139. Jason Cong
    Timing closure based on physical hierarchy. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:170-174 [Conf]
  140. Jason Cong, Jie Fang, Kei-Yong Khoo
    DUNE: a multi-layer gridless routing system with wire planning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:12-18 [Conf]
  141. Jason Cong, Joey Y. Lin, Wangning Long
    Enhanced SPFD Rewiring on Improving Rewiring Ability. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:91-96 [Conf]
  142. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
    A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:113- [Conf]
  143. Rajive Bagrodia, Zheng Li, Vikas Jha, Yuan Chen, Jason Cong
    Parallel logic level simulation of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 1994, pp:1354-1361 [Conf]
  144. Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
    LUT-based FPGA technology mapping under arbitrary net-delay models. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 1994, v:18, n:4, pp:507-516 [Journal]
  145. Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
    DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:3, pp:7-20 [Journal]
  146. Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden
    Performance optimization of VLSI interconnect layout. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:1-2, pp:1-94 [Journal]
  147. Chin-Chih Chang, Jason Cong
    Pseudopin assignment with crosstalk noise control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:598-611 [Journal]
  148. Chin-Chih Chang, Jason Cong
    An efficient approach to multilayer layer assignment with anapplication to via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:608-620 [Journal]
  149. Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan
    Multilevel global placement with congestion control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:395-409 [Journal]
  150. Chin-Chih Chang, Jason Cong, Michail Romesis, Min Xie
    Optimality and scalability study of existing placement algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:537-549 [Journal]
  151. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
    Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1424-1431 [Journal]
  152. Jason Cong
    Pin assignment with global routing for general cell designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1401-1412 [Journal]
  153. Jason Cong, Yuzheng Ding
    FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:1-12 [Journal]
  154. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
    Architecture and synthesis for on-chip multicycle communication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:550-564 [Journal]
  155. Jason Cong, Jie Fang, Kei-Yong Khoo
    Via design rule consideration in multilayer maze routing algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:215-223 [Journal]
  156. Jason Cong, Jie Fang, Kei-Yong Khoo
    DUNE-a multilayer gridless routing system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:633-647 [Journal]
  157. Jason Cong, Jie Fang, Min Xie, Yan Zhang
    MARS-a multilevel full-chip gridless routing system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:382-394 [Journal]
  158. Jason Cong, Yean-Yow Hwang
    Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1077-1090 [Journal]
  159. Jason Cong, Lei He
    Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:406-420 [Journal]
  160. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
    Interconnect sizing and spacing with consideration of couplingcapacitance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1164-1169 [Journal]
  161. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
    A provably good multilayer topological planar routing algorithm in IC layout designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:70-78 [Journal]
  162. Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
    Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:24-39 [Journal]
  163. Jason Cong, Cheng-Kok Koh, Patrick H. Madden
    Interconnect layout optimization under higher order RLC model forMCM designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1455-1463 [Journal]
  164. Jason Cong, Andrew B. Kahng, Gabriel Robins
    Matching-based methods for high-performance clock routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1157-1169 [Journal]
  165. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong
    Provably good performance-driven global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:739-752 [Journal]
  166. Jason Cong, Sung Kyu Lim
    Edge separability-based circuit clustering with application to multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:346-357 [Journal]
  167. Jason Cong, Sung Kyu Lim
    Retiming-based timing analysis with an application to mincut-based global placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1684-1692 [Journal]
  168. Jason Cong, C. L. Liu
    Over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:408-418 [Journal]
  169. Jason Cong, C. L. Liu
    On the k-layer planar subset and topological via minimization problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:972-981 [Journal]
  170. Jason Cong, Kwok-Shing Leung
    Optimal wiresizing under Elmore delay model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:321-336 [Journal]
  171. Jason Cong, Wilburt Labio, Narayanan Shivakumar
    Multiway VLSI circuit partitioning based on dual net representation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:4, pp:396-409 [Journal]
  172. Jason Cong, Patrick H. Madden
    Performance-driven routing with multiple sources. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:4, pp:410-419 [Journal]
  173. Jason Cong, David Zhigang Pan
    Interconnect performance estimation models for design planning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:739-752 [Journal]
  174. Jason Cong, David Zhigang Pan
    Wire width planning for interconnect performance optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:319-329 [Journal]
  175. Jason Cong, Bryan Preas, C. L. Liu
    Physical models and efficient algorithms for over-the-cell routing in standard cell design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:723-734 [Journal]
  176. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Fast floorplanning by look-ahead enabled recursive bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1719-1732 [Journal]
  177. Jason Cong, Chang Wu
    An efficient algorithm for performance-optimal FPGA technology mapping with retiming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:738-748 [Journal]
  178. Jason Cong, Chang Wu
    Optimal FPGA mapping and retiming with efficient initial state computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1595-1607 [Journal]
  179. Jason Cong, Martin D. F. Wong, C. L. Liu
    A new approach to three- or four-layer channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1094-1104 [Journal]
  180. Jason Cong, Songjie Xu
    Performance-driven technology mapping for heterogeneous FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1268-1281 [Journal]
  181. Kei-Yong Khoo, Jason Cong
    An efficient multilayer MCM router based on four-via routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1277-1290 [Journal]
  182. Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong
    Power modeling and characteristics of field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1712-1724 [Journal]
  183. Khe-Sing The, Martin D. F. Wong, Jason Cong
    A layout modification approach to via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:536-541 [Journal]
  184. Taku Uchino, Jason Cong
    An interconnect energy model considering coupling effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:763-776 [Journal]
  185. Deming Chen, Jason Cong, Junjuan Xu
    Optimal simultaneous module and multivoltage assignment for low power. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:362-386 [Journal]
  186. Jason Cong, Yuzheng Ding
    Combinational logic synthesis for LUT based field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:2, pp:145-204 [Journal]
  187. Jason Cong, Yean-Yow Hwang
    Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:2, pp:193-225 [Journal]
  188. Jason Cong, Lei He
    Optimal wiresizing for interconnects with multiple sources. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:4, pp:478-511 [Journal]
  189. Jason Cong, Hui Huang, Xin Yuan
    Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:3-23 [Journal]
  190. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:341-388 [Journal]
  191. Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan
    Large-scale circuit placement. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:389-430 [Journal]
  192. Gang Chen, Jason Cong
    Simultaneous placement with clustering and duplication. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:740-772 [Journal]
  193. Jason Cong, Guoling Han, Zhiru Zhang
    Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:986-997 [Journal]
  194. Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski
    Accelerating Sequential Applications on CMPs Using Core Spilling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1094-1107 [Journal]
  195. Jason Cong, Yuzheng Ding
    On area/depth trade-off in LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:137-148 [Journal]
  196. Jason Cong, Cheng-Kok Koh
    Simultaneous driver and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:408-425 [Journal]
  197. Jason Cong, Tianming Kong, Z. D. Pan
    Buffer block planning for interconnect planning and prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:929-937 [Journal]

  198. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. [Citation Graph (, )][DBLP]


  199. Thermal-Aware 3D IC Placement Via Transformation. [Citation Graph (, )][DBLP]


  200. A multilevel analytical placement for 3D ICs. [Citation Graph (, )][DBLP]


  201. Scheduling with integer time budgeting for low-power optimization. [Citation Graph (, )][DBLP]


  202. Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. [Citation Graph (, )][DBLP]


  203. High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. [Citation Graph (, )][DBLP]


  204. LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. [Citation Graph (, )][DBLP]


  205. On the futility of statistical power optimization. [Citation Graph (, )][DBLP]


  206. A variation-tolerant scheduler for better than worst-case behavioral synthesis. [Citation Graph (, )][DBLP]


  207. From milliwatts to megawatts: system level power challenge. [Citation Graph (, )][DBLP]


  208. Moore's Law: another casualty of the financial meltdown? [Citation Graph (, )][DBLP]


  209. ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. [Citation Graph (, )][DBLP]


  210. LUT-based FPGA technology mapping for reliability. [Citation Graph (, )][DBLP]


  211. Simultaneous FU and Register Binding Based on Network Flow Method. [Citation Graph (, )][DBLP]


  212. Energy efficient multiprocessor task scheduling under input-dependent variation. [Citation Graph (, )][DBLP]


  213. A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. [Citation Graph (, )][DBLP]


  214. Coordinated resource optimization in behavioral synthesis. [Citation Graph (, )][DBLP]


  215. On the k-layer planar subset and via minimization problems. [Citation Graph (, )][DBLP]


  216. Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. [Citation Graph (, )][DBLP]


  217. Lithographic aerial image simulation with FPGA-based hardwareacceleration. [Citation Graph (, )][DBLP]


  218. Pattern-based behavior synthesis for FPGA resource reduction. [Citation Graph (, )][DBLP]


  219. Mapping for better than worst-case delays in LUT-based FPGA designs. [Citation Graph (, )][DBLP]


  220. LUT-based FPGA technology mapping for reliability (abstract only). [Citation Graph (, )][DBLP]


  221. Revisiting bitwidth optimizations. [Citation Graph (, )][DBLP]


  222. Synthesis of reconfigurable high-performance multicore systems. [Citation Graph (, )][DBLP]


  223. Bit-level optimization for high-level synthesis and FPGA-based acceleration. [Citation Graph (, )][DBLP]


  224. Accelerating Monte Carlo based SSTA using FPGA. [Citation Graph (, )][DBLP]


  225. Customizable domain-specific computing. [Citation Graph (, )][DBLP]


  226. CMP network-on-chip overlaid with multi-band RF-interconnect. [Citation Graph (, )][DBLP]


  227. MC-Sim: an efficient simulation tool for MPSoC designs. [Citation Graph (, )][DBLP]


  228. Fault tolerant placement and defect reconfiguration for nano-FPGAs. [Citation Graph (, )][DBLP]


  229. Scheduling with soft constraints. [Citation Graph (, )][DBLP]


  230. Automatic memory partitioning and scheduling for throughput and power optimization. [Citation Graph (, )][DBLP]


  231. A rigorous framework for convergent net weighting schemes in timing-driven placement. [Citation Graph (, )][DBLP]


  232. Parallel multi-level analytical global placement on graphics processing units. [Citation Graph (, )][DBLP]


  233. Fine grain 3D integration for microarchitecture design through cube packing exploration. [Citation Graph (, )][DBLP]


  234. High-performance CUDA kernel execution on FPGAs. [Citation Graph (, )][DBLP]


  235. Behavior-level observability don't-cares and application to low-power behavioral synthesis. [Citation Graph (, )][DBLP]


  236. Highly efficient gradient computation for density-constrained analytical placement methods. [Citation Graph (, )][DBLP]


  237. RF interconnects for communications on-chip. [Citation Graph (, )][DBLP]


  238. Robust gate sizing via mean excess delay minimization. [Citation Graph (, )][DBLP]


  239. An analytical placer for mixed-size 3D placement. [Citation Graph (, )][DBLP]


  240. Power reduction of CMP communication networks via RF-interconnects. [Citation Graph (, )][DBLP]


  241. A scalable micro wireless interconnect structure for CMPs. [Citation Graph (, )][DBLP]


  242. Multiband RF-interconnect for reconfigurable network-on-chip communications. [Citation Graph (, )][DBLP]


  243. A new generation of C-base synthesis tool and domain-specific computing. [Citation Graph (, )][DBLP]


  244. FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. [Citation Graph (, )][DBLP]


  245. The Last Byte: The HLS tipping point. [Citation Graph (, )][DBLP]


  246. NSF Workshop on EDA: Past, Present, and Future (Part 1). [Citation Graph (, )][DBLP]


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