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Publications of Author

1. Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
   Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:223-230 [Conf]
   
2. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
   Introspective 3D chips. [Citation Graph (0, 0)][DBLP]
   ASPLOS, 2006, pp:264-273 [Conf]
   
3. Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee
   Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:884-887 [Conf]
   
4. Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
   A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:991-996 [Conf]
   
5. Sheng-Chih Lin, Kaustav Banerjee
   An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:568-574 [Conf]
   
6. Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
   A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:411-416 [Conf]
   
7. Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee
   A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. [Citation Graph (0, 0)][DBLP]
   ISQED, 2004, pp:259-264 [Conf]
   
8. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
   3D Integration for Introspection. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2007, v:27, n:1, pp:77-83 [Journal]