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Navin Srivastava: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
    Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:223-230 [Conf]
  2. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
    Introspective 3D chips. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:264-273 [Conf]
  3. Kaustav Banerjee, Navin Srivastava
    Are carbon nanotubes the future of VLSI interconnections? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:809-814 [Conf]
  4. Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
    A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:991-996 [Conf]
  5. Navin Srivastava, Kaustav Banerjee
    Performance analysis of carbon nanotube interconnects for VLSI applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:383-390 [Conf]
  6. Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
    A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:411-416 [Conf]
  7. Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
    Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:346-351 [Conf]
  8. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
    3D Integration for Introspection. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:77-83 [Journal]

  9. High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. [Citation Graph (, )][DBLP]


  10. Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. [Citation Graph (, )][DBLP]


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