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Chung-Kuan Cheng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    A General Purpose Multiple Way Partitioning Algorithm. [Citation Graph (2, 0)][DBLP]
    DAC, 1991, pp:421-426 [Conf]
  2. Hongyu Chen, Chung-Kuan Cheng
    A multi-level transmission line network approach for multi-giga hertz clock distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:103-106 [Conf]
  3. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang
    Optimal planning for mesh-based power distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:444-449 [Conf]
  4. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    A buffer planning algorithm with congestion optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:615-620 [Conf]
  5. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
    Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:527-532 [Conf]
  6. C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
    Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  7. Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng
    A multiple level network approach for clock skew minimization with process variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:263-268 [Conf]
  8. Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    VLSI floorplanning with boundary constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:509-514 [Conf]
  9. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Buffer allocation algorithm with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:621-623 [Conf]
  10. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:387-392 [Conf]
  11. Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Performance driven multiple-source bus synthesis using buffer insertion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  12. Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen
    A Performance-Driven I/O Pin Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:129-132 [Conf]
  13. Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng
    A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:463-468 [Conf]
  14. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton
    Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:73-78 [Conf]
  15. Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng
    Integrated algorithmic logical and physical design of integer multiplier. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1014-1017 [Conf]
  16. Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham
    Constructing zero-deficiency parallel prefix adder of minimum depth. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:883-888 [Conf]
  17. Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh
    Efficient transient simulation for transistor-level analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:240-243 [Conf]
  18. Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh
    An unconditional stable general operator splitting method for transistor level transient analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:428-433 [Conf]
  19. Yi Zhu, Tong Lee Chen, Wanping Zhang, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng
    Noninvasive Study of the Human Heart using Independent Component Analysis. [Citation Graph (0, 0)][DBLP]
    BIBE, 2006, pp:340-347 [Conf]
  20. Robert C. Carden IV, Chung-Kuan Cheng
    A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:316-321 [Conf]
  21. Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska
    Fast post-placement rewiring using easily detectable functional symmetries. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:286-289 [Conf]
  22. Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
    An algebraic multigrid solver for analytical placement with layout based clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:794-799 [Conf]
  23. Chung-Kuan Cheng, David N. Deutsch
    Improved Channel Routing by Via Minimization and Shifting. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:677-680 [Conf]
  24. Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
    Circuit Partitioning for Huge Logic Emulation Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:244-249 [Conf]
  25. Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura
    An O-Tree Representation of Non-Slicing Floorplan and Its Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:268-273 [Conf]
  26. Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau
    A Wire Length Estimation Technique Utilizing Neighborhood Density Equations. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:57-61 [Conf]
  27. Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau
    Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:531-536 [Conf]
  28. Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
    FARM: An Efficient Feed-Through Pin Assignment Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:530-535 [Conf]
  29. Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
    Performance-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:177-181 [Conf]
  30. Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng
    Communication latency aware low power NoC synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:574-579 [Conf]
  31. Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
    An Efficient Timing-Driven Global Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:596-600 [Conf]
  32. Ming-Ter Kuo, Chung-Kuan Cheng
    A Network Flow Approach for Hierarchical Tree Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:512-517 [Conf]
  33. Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng
    Network Partitioning into Tree Hierarchies. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:477-482 [Conf]
  34. Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng
    New Spectral Linear Placement and Clustering Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:88-93 [Conf]
  35. John Lillis, Chung-Kuan Cheng
    Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:214-219 [Conf]
  36. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho
    New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:395-400 [Conf]
  37. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Dynamic global buffer planning optimization based on detail block locating and congestion analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:806-811 [Conf]
  38. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:770-775 [Conf]
  39. Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng
    Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:274-279 [Conf]
  40. Fang-Jou Liu, Chung-Kuan Cheng
    Extending Moment Computation to 2-Port Circuit Representations. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:473-476 [Conf]
  41. Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu
    Performance-Driven Partitioning Using a Replication Graph Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:206-210 [Conf]
  42. Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng
    Data Flow Partitioning for Clock Period and Latency Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:658-663 [Conf]
  43. Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng
    Block placement with symmetry constraints based on the O-tree non-slicing representation. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:464-467 [Conf]
  44. Zhanhai Qin, Chung-Kuan Cheng
    Realizable parasitic reduction using generalized Y-Delta transformation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:220-225 [Conf]
  45. Rui Shi, Chung-Kuan Cheng
    Efficient escape routing for hexagonal array of high density I/Os. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1003-1008 [Conf]
  46. Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
    Cluster Refinement for Block Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:762-765 [Conf]
  47. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
    Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:395-400 [Conf]
  48. Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng
    Power network analysis using an adaptive algebraic multigrid approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:105-108 [Conf]
  49. Jianmin Li, Chung-Kuan Cheng
    Routability improvement using dynamic interconnect architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 1995, pp:61-67 [Conf]
  50. Jianhua Liu, Michael Chang, Chung-Kuan Cheng
    An iterative division algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:83-89 [Conf]
  51. Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
    Fast adders in modern FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:250- [Conf]
  52. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Simultaneous Routing and Buffer Insertion for High Performance Interconnect. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:148-153 [Conf]
  53. Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita
    An efficient algorithm for the net matching problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:640-644 [Conf]
  54. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
    The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:13-20 [Conf]
  55. Jae Chung, Chung-Kuan Cheng
    Skew sensitivity minimization of buffered clock tree. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:280-283 [Conf]
  56. Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:8-12 [Conf]
  57. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Optimal wire sizing and buffer insertion for low power and a generalized delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:138-143 [Conf]
  58. Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng
    A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:229-234 [Conf]
  59. Jianmin Li, John Lillis, Chung-Kuan Cheng
    Linear decomposition algorithm for VLSI design applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:223-228 [Conf]
  60. Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku
    Performance-driven partitioning using retiming and replication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:296-299 [Conf]
  61. Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng
    An Algorithmic Approach for Generic Parallel Adders. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:734-740 [Conf]
  62. Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher
    Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:222-228 [Conf]
  63. Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng
    RLC interconnect delay estimation via moments of amplitude and phase response. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:208-213 [Conf]
  64. So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
    An optimal probe testing algorthm for the connectivity verification of MCM substrates. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:264-267 [Conf]
  65. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    A probabilistic multicommodity-flow solution to circuit clustering problems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:428-431 [Conf]
  66. Yen-Chuen Wei, Chung-Kuan Cheng
    A Two-Level Two-Way Partitioning Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:516-519 [Conf]
  67. Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:153-157 [Conf]
  68. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
    Improving the efficiency of static timing analysis with false paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:527-531 [Conf]
  69. Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald Graham, Mike Hutton, Chung-Kuan Cheng
    Timing model reduction for hierarchical timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:415-422 [Conf]
  70. Renshen Wang, Rui Shi, Chung-Kuan Cheng
    Layer minimization of escape routing in area array packaging. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:815-819 [Conf]
  71. Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng
    Simple tree-construction heuristics for the fanout problem . [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:671-679 [Conf]
  72. Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris
    Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:497-502 [Conf]
  73. Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
    Physical Planning Of On-Chip Interconnect Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:30-35 [Conf]
  74. Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham
    Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:180-186 [Conf]
  75. Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng
    Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:111-118 [Conf]
  76. Chung-Kuan Cheng, T. C. Hu
    Ancestor Tree for Arbitrary Multi-Terminal Cut Functions. [Citation Graph (0, 0)][DBLP]
    IPCO, 1990, pp:115-127 [Conf]
  77. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
    VLSI block placement with alignment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6222-6225 [Conf]
  78. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Evaluating a bounded slice-line grid assignment in O(nlogn) time. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:708-711 [Conf]
  79. Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng
    Finite State Machine Decomposition for I/O Minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1061-1064 [Conf]
  80. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
    Performance constrained floorplanning based on partial clustering [IC layout]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1863-1866 [Conf]
  81. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
    Arbitrary convex and concave rectilinear block packing based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:493-496 [Conf]
  82. Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Optimization of power dissipation and skew sensitivity in clock buffer synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:179-184 [Conf]
  83. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng
    Integrating dynamic thermal via planning with 3D floorplanning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:178-185 [Conf]
  84. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    An integrated floorplanning with an efficient buffer planning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:136-142 [Conf]
  85. Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie
    Rectilinear block packing using O-tree representation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:156-161 [Conf]
  86. Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura
    An enhanced perturbing algorithm for floorplan design using the O-tree representation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:168-173 [Conf]
  87. Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
    Rectilinear block placement using sequence-pair. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:173-178 [Conf]
  88. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
    Unified quadratic programming approach for mixed mode placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:193-199 [Conf]
  89. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
    Revisiting floorplan representations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:138-143 [Conf]
  90. Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    ECBL: an extended corner block list with solution space including optimum placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:150-155 [Conf]
  91. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
    Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:628-633 [Conf]
  92. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
    Buffer Planning Algorithm Based on Partial Clustered Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:213-219 [Conf]
  93. Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
    Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:251-256 [Conf]
  94. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang
    Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:71-76 [Conf]
  95. Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng
    Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:85-89 [Conf]
  96. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
    Interconnect implications of growth-based structural models for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:99-106 [Conf]
  97. Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham
    A hierarchical three-way interconnect architecture for hexagonal processors. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:133-139 [Conf]
  98. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:387-392 [Conf]
  99. Chung-Kuan Cheng, T. C. Hu
    Maximum Concurrent Flows and Minimum Cuts. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1992, v:8, n:3, pp:233-249 [Journal]
  100. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with abutment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:65-77 [Journal]
  101. Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai
    An Optimum Placement Search Algorithm Based on Extended Corner Block List. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2002, v:17, n:6, pp:699-707 [Journal]
  102. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
    Fast Evaluation of Bounded Slice-Line Grid. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:6, pp:973-980 [Journal]
  103. Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    General Floorplans with L/T-Shaped Blocks Using Corner Block List. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:922-926 [Journal]
  104. Chung-Kuan Cheng, S. Z. Yao, T. C. Hu
    The Orientation of Modules Based on Graph Decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:774-780 [Journal]
  105. Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng
    A global router with a theoretical bound on the optimal solution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:208-216 [Journal]
  106. Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi
    Solving the net matching problem in high-performance chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:902-911 [Journal]
  107. Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
    Fast postplacement optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:102-118 [Journal]
  108. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
    The Y architecture for on-chip interconnect: analysis and methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:588-599 [Journal]
  109. Chung-Kuan Cheng, Ximtie Deng, Yuh-Zen Liao, So-Zen Yao
    Symbolic layout compaction under conditional design rules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:475-486 [Journal]
  110. Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien
    Geometric compaction on channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:115-127 [Journal]
  111. Chung-Kuan Cheng, Ernest S. Kuh
    Module Placement Based on Resistive Network Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:218-225 [Journal]
  112. Chung-Kuan Cheng, Yen-Chuen A. Wei
    An improved two-way partitioning algorithm with stable performance [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1502-1511 [Journal]
  113. Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
    Local ratio cut and set covering partitioning for huge logic emulation systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1085-1092 [Journal]
  114. Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau
    A wire length estimation technique utilizing neighborhood density equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:912-922 [Journal]
  115. Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura
    Floorplanning using a tree representation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:281-289 [Journal]
  116. Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
    TIGER: an efficient timing-driven global router for gate array and standard cell layout design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1323-1331 [Journal]
  117. Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu
    UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:358-365 [Journal]
  118. Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu
    A replication cut for two-way partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:623-630 [Journal]
  119. John Lillis, Chung-Kuan Cheng
    Timing optimization for multisource nets: characterization andoptimal repeater insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:322-331 [Journal]
  120. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
    Buffer planning as an Integral part of floorplanning with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:609-621 [Journal]
  121. Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng
    Performance driven bus buffer insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:4, pp:429-437 [Journal]
  122. Yen-Chuen Wei, Chung-Kuan Cheng
    Ratio cut partitioning for hierarchical designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:911-921 [Journal]
  123. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area minimization of power distribution network using efficient nonlinear programming techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1086-1094 [Journal]
  124. Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
    Sequence-pair approach for rectilinear module placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:484-493 [Journal]
  125. So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
    A multi-probe approach for MCM substrate testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:110-121 [Journal]
  126. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
    A cell-based hierarchical pitchmatching compaction using minimal LP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:523-526 [Journal]
  127. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    A general purpose, multiple-way partitioning algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1480-1488 [Journal]
  128. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Optimization by iterative improvement: an experimental evaluation on two-way partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:145-153 [Journal]
  129. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Circuit clustering using a stochastic flow injection method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:154-162 [Journal]
  130. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway compaction using corner block list and its applications with rectilinear blocks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:199-211 [Journal]
  131. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
    Floorplan representations: Complexity and connections. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:55-80 [Journal]
  132. Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham
    On the construction of zero-deficiency parallel prefix circuits with minimum depth. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:387-409 [Journal]
  133. Wanping Zhang, Chung-Kuan Cheng
    Incremental Power Impedance Optimization Using Vector Fitting Modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2439-2442 [Conf]
  134. He Peng, Chung-Kuan Cheng
    Fast Transient Simulation of Lossy Transmission Lines. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2706-2709 [Conf]
  135. Jianmin Li, Chung-Kuan Cheng
    Routability improvement using dynamic interconnect architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:498-501 [Journal]
  136. Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel
    Block-oriented programmable design with switching network interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:45-53 [Journal]
  137. Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee
    Physical models and algorithms for optoelectronic MCM layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:124-135 [Journal]
  138. Nan-Chi Chou, Chung-Kuan Cheng
    On general zero-skew clock net construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:141-146 [Journal]
  139. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
    Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:177-189 [Journal]

  140. Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders. [Citation Graph (, )][DBLP]


  141. Noise minimization during power-up stage for a multi-domain power network. [Citation Graph (, )][DBLP]


  142. An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. [Citation Graph (, )][DBLP]


  143. Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. [Citation Graph (, )][DBLP]


  144. Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. [Citation Graph (, )][DBLP]


  145. High performance current-mode differential logic. [Citation Graph (, )][DBLP]


  146. Timing-power optimization for mixed-radix Ling adders by integer linear programming. [Citation Graph (, )][DBLP]


  147. High performance on-chip differential signaling using passive compensation for global communication. [Citation Graph (, )][DBLP]


  148. Parallel transistor level circuit simulation using domain decomposition methods. [Citation Graph (, )][DBLP]


  149. Exploring Cardioneural Signals from Noninvasive ECG Measurement. [Citation Graph (, )][DBLP]


  150. Low power passive equalizer optimization using tritonic step response. [Citation Graph (, )][DBLP]


  151. Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. [Citation Graph (, )][DBLP]


  152. Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. [Citation Graph (, )][DBLP]


  153. Reliability aware through silicon via planning for 3D stacked ICs. [Citation Graph (, )][DBLP]


  154. Parallel transistor level full-chip circuit simulation. [Citation Graph (, )][DBLP]


  155. On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. [Citation Graph (, )][DBLP]


  156. Octilinear redistributive routing in bump arrays. [Citation Graph (, )][DBLP]


  157. Bus via reduction based on floorplan revising. [Citation Graph (, )][DBLP]


  158. Low Power Passive Equalizer Design for Computer Memory Links. [Citation Graph (, )][DBLP]


  159. Efficient and accurate eye diagram prediction for high speed signaling. [Citation Graph (, )][DBLP]


  160. Advancing supercomputer performance through interconnection topology synthesis. [Citation Graph (, )][DBLP]


  161. A novel fixed-outline floorplanner with zero deadspace for hierarchical design. [Citation Graph (, )][DBLP]


  162. Passive compensation for high performance inter-chip communication. [Citation Graph (, )][DBLP]


  163. FPGA global routing architecture optimization using a multicommodity flow approach. [Citation Graph (, )][DBLP]


  164. Fast power network analysis with multiple clock domains. [Citation Graph (, )][DBLP]


  165. On-chip high performance signaling using passive compensation. [Citation Graph (, )][DBLP]


  166. 3-D floorplanning using labeled tree and dual sequences. [Citation Graph (, )][DBLP]


  167. Physical synthesis of bus matrix for high bandwidth low power on-chip communications. [Citation Graph (, )][DBLP]


  168. Efficient power network analysis with complete inductive modeling. [Citation Graph (, )][DBLP]


  169. Clock Skew Analysis via Vector Fitting in Frequency Domain. [Citation Graph (, )][DBLP]


  170. Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network. [Citation Graph (, )][DBLP]


  171. Design methodology of high performance on-chip global interconnect using terminated transmission-line. [Citation Graph (, )][DBLP]


  172. Worst-case noise prediction with non-zero current transition times for early power distribution system verification. [Citation Graph (, )][DBLP]


  173. Predicting the worst-case voltage violation in a 3D power network. [Citation Graph (, )][DBLP]


  174. Prediction of high-performance on-chip global interconnection. [Citation Graph (, )][DBLP]


  175. On the bound of time-domain power supply noise based on frequency-domain target impedance. [Citation Graph (, )][DBLP]


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