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G. Surendra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Subhasis Banerjee, G. Surendra, S. K. Nandy
    Exploiting program execution phases to trade power and performance for media workload. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:387-389 [Conf]
  2. G. Surendra, Subhasis Banerjee, S. K. Nandy
    Power-performance trade-off using pipeline delays. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:384-386 [Conf]
  3. G. Surendra, Subhasis Banerjee, S. K. Nandy
    Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10784-10789 [Conf]
  4. G. Surendra, S. K. Nandy, Paul Sathya
    ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:85-90 [Conf]
  5. G. Surendra, Subhasis Banerjee, S. K. Nandy
    On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:88-95 [Conf]
  6. G. Surendra, Subhasis Banerjee, S. K. Nandy
    On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2003, v:31, n:6, pp:469-487 [Journal]

  7. Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. [Citation Graph (, )][DBLP]


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