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Yao-Wen Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tai-Chen Chen, Yao-Wen Chang
    Multilevel full-chip gridless routing considering optical proximity correction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1160-1163 [Conf]
  2. Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin
    A novel framework for multilevel full-chip gridless routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:636-641 [Conf]
  3. Yi-Hui Cheng, Yao-Wen Chang
    Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:624-627 [Conf]
  4. Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
    IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:366-371 [Conf]
  5. Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang
    Placement with symmetry constraints for analog layout design using TCG-S. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1135-1137 [Conf]
  6. Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang
    Simultaneous block and I/O buffer floorplanning for flip-chip design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:213-218 [Conf]
  7. Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
    Layout techniques for on-chip interconnect inductance reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:269-273 [Conf]
  8. Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang
    SoC test scheduling using the B-tree based floorplanning technique. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1188-1191 [Conf]
  9. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen
    Temporal floorplanning using 3D-subTCG. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:725-730 [Conf]
  10. Yao-Wen Chang, Yu-Tsang Chang
    An architecture-driven metric for simultaneous placement and global routing for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:567-572 [Conf]
  11. Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu
    B*-Trees: a new representation for non-slicing floorplans. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:458-463 [Conf]
  12. Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han
    Novel full-chip gridless routing considering double-via insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:755-760 [Conf]
  13. Chung-Ping Chen, Yao-Wen Chang, D. F. Wong
    Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:405-408 [Conf]
  14. Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen
    Multilevel full-chip routing for the X-based architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:597-602 [Conf]
  15. Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
    Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:90-95 [Conf]
  16. Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang
    Multilevel floorplanning/placement for large-scale modules using B*-trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:812-817 [Conf]
  17. Jai-Ming Lin, Yao-Wen Chang
    TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:764-769 [Conf]
  18. Jai-Ming Lin, Yao-Wen Chang
    TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:842-847 [Conf]
  19. Bor-Yiing Su, Yao-Wen Chang
    An exact jumper insertion algorithm for antenna effect avoidance/fixing. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:325-328 [Conf]
  20. Su-Wei Wu, Yao-Wen Chang
    Efficient power/ground network analysis for power integrity-driven design methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:177-180 [Conf]
  21. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
    Placement of digital microfluidic biochips using the t-tree formulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:931-934 [Conf]
  22. Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
    Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:69-77 [Conf]
  23. Yao-Wen Chang, D. F. Wong, C. K. Wong
    Universal Switch-Module Design for Symmetric-Array-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:80-86 [Conf]
  24. Guang-Ming Wu, Michael Shyu, Yao-Wen Chang
    Universal Switch Blocks for Three-Dimensional FPGA Design. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:254- [Conf]
  25. Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
    IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:159-164 [Conf]
  26. Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
    Graph matching-based algorithms for FPGA segmentation design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:34-39 [Conf]
  27. Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
    A new global routing algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:356-361 [Conf]
  28. Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
    A clustering- and probability-based approach for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:364-369 [Conf]
  29. Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang
    A routing algorithm for flip-chip design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:753-758 [Conf]
  30. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee
    A Fast Crosstalk- and Performance-Driven Multilevel Routing System. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:382-387 [Conf]
  31. Shih-Ping Lin, Yao-Wen Chang
    A novel framework for multilevel routing considering routability and performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:44-50 [Conf]
  32. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
    Temporal floorplanning using the T-tree formulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:300-305 [Conf]
  33. Kai Zhu, D. F. Wong, Yao-Wen Chang
    Switch module design with application to two-dimensional segmentation design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:480-485 [Conf]
  34. Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
    A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:187-192 [Conf]
  35. Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo
    Current path analysis for electrostatic discharge protection. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:510-515 [Conf]
  36. Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
    Voltage island aware floorplanning for power and timing optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:389-394 [Conf]
  37. Zhe-Wei Jiang, Yao-Wen Chang
    An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:669-674 [Conf]
  38. Yao-Wen Chang, D. F. Wong, C. K. Wong
    FPGA global routing based on a new congestion metric. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:372-0 [Conf]
  39. Yao-Wen Chang, D. F. Wong, C. K. Wong
    Design and analysis of FPGA/FPIC switch modules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:394-401 [Conf]
  40. Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
    Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:192-198 [Conf]
  41. Meng-Chen Wu, Yao-Wen Chang
    Placement with Alignment and Performance Constraints Using the B*-Tree Representation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:568-571 [Conf]
  42. Song-Ra Pan, Yao-Wen Chang
    Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:581-584 [Conf]
  43. Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang
    Generic Universal Switch Blocks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:311-314 [Conf]
  44. Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang
    Rectilinear Block Placement Using B*-Trees. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:351-356 [Conf]
  45. Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
    An Algorithm for Dynamically Reconfigurable FPGA Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:501-504 [Conf]
  46. Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
    Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:335-347 [Conf]
  47. Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
    RLC effects on worst-case switching pattern for on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:945-948 [Conf]
  48. Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
    Joint exploration of architectural and physical design spaces with thermal consideration. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:123-126 [Conf]
  49. Guang-Ming Wu, Yao-Wen Chang
    Switch-matrix architecture and routing for FPDs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:158-163 [Conf]
  50. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
    Multilevel routing with antenna avoidance. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:34-40 [Conf]
  51. Tung-Chieh Chen, Yao-Wen Chang
    Modern floorplanning based on fast simulated annealing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:104-112 [Conf]
  52. Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang
    NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:236-238 [Conf]
  53. Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
    NTUplace2: a hybrid placer using partitioning and analytical techniques. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:215-217 [Conf]
  54. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
    Optimal reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:128-133 [Conf]
  55. Chen-Wei Liu, Yao-Wen Chang
    Floorplan and power/ground network co-synthesis for fast design convergence. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:86-93 [Conf]
  56. Bor-Yiing Su, Yao-Wen Chang, Jiang Hu
    An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:56-63 [Conf]
  57. Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang
    Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:523-528 [Conf]
  58. Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen
    Reconfigurable Platform for Content Science Research. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:481-486 [Conf]
  59. Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
    Multilevel full-chip routing with testability and yield enhancement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:29-36 [Conf]
  60. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
    Multilevel routing with jumper insertion for antenna avoidance. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:4, pp:420-432 [Journal]
  61. Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang
    A clustering- and probability-based approach for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:2, pp:245-265 [Journal]
  62. Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang
    Comment on Generic Universal Switch Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:1, pp:93-96 [Journal]
  63. Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang
    Generic Universal Switch Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:4, pp:348-359 [Journal]
  64. Guang-Ming Wu, Yao-Wen Chang
    Quasi-Universal Switch Matrices for FPD Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:10, pp:1107-1122 [Journal]
  65. Yao-Wen Chang, Shih-Ping Lin
    MR: a new framework for multilevel full-chip routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:793-800 [Journal]
  66. Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong
    Matching-based algorithm for FPGA channel segmentation design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:784-791 [Journal]
  67. Tung-Chieh Chen, Yao-Wen Chang
    Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:637-650 [Journal]
  68. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee
    Crosstalk- and performance-driven multilevel full-chip routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:869-878 [Journal]
  69. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
    Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:999-1010 [Journal]
  70. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
    Simultaneous floor plan and buffer-block optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:694-703 [Journal]
  71. Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
    IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2513-2525 [Journal]
  72. Jai-Ming Lin, Yao-Wen Chang
    TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:968-980 [Journal]
  73. Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan
    Algorithms for an FPGA switch module routing problem with application to global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:32-46 [Journal]
  74. Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
    Generic ILP-based approaches for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1266-1274 [Journal]
  75. Yao-Wen Chang, D. F. Wong, C. K. Wong
    Universal switch modules for FPGA design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:1, pp:80-101 [Journal]
  76. Yao-Wen Chang, Kai Zhu, D. F. Wong
    Timing-driven routing for symmetrical array-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:433-450 [Journal]
  77. Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
    Analysis of FPGA/FPIC switch modules. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:11-37 [Journal]
  78. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
    Reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:88-103 [Journal]
  79. Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang
    Rectilinear block placement using B*-trees. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:188-202 [Journal]
  80. Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
    Performance-driven placement for dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:628-642 [Journal]
  81. Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
    Timing modeling and optimization under the transmission line model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:28-41 [Journal]
  82. Jai-Ming Lin, Yao-Wen Chang
    TCG: A transitive closure graph-based representation for general floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:288-292 [Journal]
  83. Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang
    A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:887-890 [Conf]
  84. Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang
    An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:606-611 [Conf]
  85. Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu
    MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:447-452 [Conf]
  86. Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai
    Inductance extraction for general interconnect structures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  87. Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
    X-architecture placement based on effective wire models. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:87-94 [Conf]
  88. Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
    Efficient obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:127-134 [Conf]
  89. Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang
    A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:148-159 [Conf]
  90. I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang
    Statistical circuit optimization considering device andinterconnect process variations. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:47-54 [Conf]
  91. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
    Temporal floorplanning using the three-dimensional transitive closure subGraph. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
  92. Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
    Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:886-901 [Journal]
  93. Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin
    Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:679-686 [Journal]

  94. High-performance global routing with fast overflow reduction. [Citation Graph (, )][DBLP]


  95. Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. [Citation Graph (, )][DBLP]


  96. Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. [Citation Graph (, )][DBLP]


  97. A progressive-ILP based routing algorithm for cross-referencing biochips. [Citation Graph (, )][DBLP]


  98. Predictive formulae for OPC with applications to lithography-friendly routing. [Citation Graph (, )][DBLP]


  99. Thermal-driven analog placement considering device matching. [Citation Graph (, )][DBLP]


  100. Flip-chip routing with unified area-I/O pad assignments for package-board co-design. [Citation Graph (, )][DBLP]


  101. Spare-cell-aware multilevel analytical placement. [Citation Graph (, )][DBLP]


  102. ILP-based pin-count aware design methodology for microfluidic biochips. [Citation Graph (, )][DBLP]


  103. Fast timing-model independent buffered clock-tree synthesis. [Citation Graph (, )][DBLP]


  104. Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips. [Citation Graph (, )][DBLP]


  105. Pulsed-latch aware placement for timing-integrity optimization. [Citation Graph (, )][DBLP]


  106. Novel wire density driven full-chip routing for CMP variation control. [Citation Graph (, )][DBLP]


  107. ECO timing optimization using spare cells. [Citation Graph (, )][DBLP]


  108. Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. [Citation Graph (, )][DBLP]


  109. An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. [Citation Graph (, )][DBLP]


  110. An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. [Citation Graph (, )][DBLP]


  111. BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. [Citation Graph (, )][DBLP]


  112. Multi-layer global routing considering via and wire capacities. [Citation Graph (, )][DBLP]


  113. Constraint graph-based macro placement for modern mixed-size circuit designs. [Citation Graph (, )][DBLP]


  114. Area-I/O flip-chip routing for chip-package co-design. [Citation Graph (, )][DBLP]


  115. Routing for chip-package-board co-design considering differential pairs. [Citation Graph (, )][DBLP]


  116. An efficient pre-assignment routing algorithm for flip-chip designs. [Citation Graph (, )][DBLP]


  117. Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. [Citation Graph (, )][DBLP]


  118. Simultaneous layout migration and decomposition for double patterning technology. [Citation Graph (, )][DBLP]


  119. BIST design optimization for large-scale embedded memory cores. [Citation Graph (, )][DBLP]


  120. 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. [Citation Graph (, )][DBLP]


  121. RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. [Citation Graph (, )][DBLP]


  122. Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  123. Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. [Citation Graph (, )][DBLP]


  124. Density gradient minimization with coupling-constrained dummy fill for CMP control. [Citation Graph (, )][DBLP]


  125. Metal-density driven placement for cmp variation and routability. [Citation Graph (, )][DBLP]


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