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Aditya Bansal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
    Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:237-242 [Conf]
  2. Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy
    A high density, carbon nanotube capacitor for decoupling applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:935-938 [Conf]
  3. Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy
    Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:983-988 [Conf]
  4. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-gate SOI devices for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:217-224 [Conf]
  5. Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
    Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:583-586 [Conf]
  6. Aditya Bansal, Kaushik Roy
    Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:1-4 [Conf]
  7. Hari Ananthan, Aditya Bansal, Kaushik Roy
    FinFET SRAM - Device and Circuit Design Considerations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:511-516 [Conf]
  8. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-Gate SOI Devices for Low-Power and High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:445-452 [Conf]
  9. Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
    High Performance and Low Power Electronics on Flexible Substrate. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:274-275 [Conf]

  10. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]

  11. Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. [Citation Graph (, )][DBLP]

  12. Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. [Citation Graph (, )][DBLP]

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