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Kaushik Roy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
    Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:237-242 [Conf]
  2. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:893-898 [Conf]
  3. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Dynamic Noise Analysis with Capacitive and Inductive Coupling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:65-70 [Conf]
  4. Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
    Speed binning aware design methodology to improve profit under parameter variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:712-717 [Conf]
  5. Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:665-670 [Conf]
  6. Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy
    Adaptive supply voltage technique for low swing interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:284-287 [Conf]
  7. Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:158-163 [Conf]
  8. Yibin Ye, Kaushik Roy, Rolf Drechsler
    Power Consumption in XOR-Based Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:299-302 [Conf]
  9. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:170-175 [Conf]
  10. Swarup Bhunia, Hai Li, Kaushik Roy
    A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:157-0 [Conf]
  11. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:404-409 [Conf]
  12. Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy
    Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:176-181 [Conf]
  13. Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy
    Design Verification and Robust Design Technique for Cross-Talk Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:449-0 [Conf]
  14. Cheng-Yi Chen, Soonkeon Kwon, Kaushik Roy
    Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array. [Citation Graph (0, 0)][DBLP]
    Communications in Computing, 2004, pp:167-176 [Conf]
  15. Hari Ananthan, Kaushik Roy
    A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:413-418 [Conf]
  16. Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
    Leakage in nano-scale technologies: mechanisms, impact and design considerations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:6-11 [Conf]
  17. Amit Agarwal, Hai Li, Kaushik Roy
    DRG-cache: a data retention gated-ground cache for low power. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:473-478 [Conf]
  18. Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
    A novel synthesis approach for active leakage power reduction using dynamic supply gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:479-484 [Conf]
  19. Swarup Bhunia, Kaushik Roy, Jaume Segura
    A novel wavelet transform based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:361-366 [Conf]
  20. Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy
    A high density, carbon nanotube capacitor for decoupling applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:935-938 [Conf]
  21. Zhanping Chen, Kaushik Roy
    A Power Macromodeling Technique Based on Power Sensitivity. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:678-683 [Conf]
  22. Seung Hoon Choi, Kaushik Roy, Florentin Dartu
    Timed pattern generation for noise-on-delay calculation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:870-873 [Conf]
  23. Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy
    Test challenges for deep sub-micron technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:142-149 [Conf]
  24. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Novel sizing algorithm for yield improvement under process variation in nanometer technology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:454-459 [Conf]
  25. Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy
    Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:971-976 [Conf]
  26. Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
    Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:442-445 [Conf]
  27. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
    Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:169-174 [Conf]
  28. Sudip Nag, Kaushik Roy
    Iterative Wirability and Performance Improvement for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:321-325 [Conf]
  29. Yibin Ye, Kaushik Roy
    A Graph-Based Synthesis Algorithm for AND/XOR Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:107-112 [Conf]
  30. Kaushik Roy, Jacob A. Abraham
    A Novel Approach to Accurate Timing Verification Using RTL Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:638-641 [Conf]
  31. Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
    Dynamic noise analysis in precharge-evaluate circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:243- [Conf]
  32. Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
    Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:489-494 [Conf]
  33. Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
    Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:430-435 [Conf]
  34. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:846-851 [Conf]
  35. Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy
    An adaptive window-based susceptance extraction and its efficient implementation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:728-731 [Conf]
  36. Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
    Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10778-10783 [Conf]
  37. Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
    Low power synthesis of dynamic logic circuits using fine-grained clock gating. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:862-867 [Conf]
  38. Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
    A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1136-1141 [Conf]
  39. Mark M. Budnik, Kaushik Roy
    Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1116-1121 [Conf]
  40. Swarup Bhunia, Kaushik Roy
    Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1118- [Conf]
  41. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:704-705 [Conf]
  42. Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
    Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10096-10103 [Conf]
  43. Seung Hoon Choi, Kaushik Roy
    A New Crosstalk Noise Model for DOMINO Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11112-11113 [Conf]
  44. Hunsoo Choo, Khurram Muhammad, Kaushik Roy
    MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10700-10705 [Conf]
  45. Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy
    Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:931-937 [Conf]
  46. Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy
    Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:983-988 [Conf]
  47. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
    Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:926-931 [Conf]
  48. Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy
    Statistical Timing Analysis using Levelized Covariance Propagation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:764-769 [Conf]
  49. Chris H. Kim, Kaushik Roy
    Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:163-167 [Conf]
  50. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:224-229 [Conf]
  51. Cassondra Neau, Khurram Muhammad, Kaushik Roy
    Low complexity FIR filters using factorization of perturbed coefficients. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:268-272 [Conf]
  52. Jongsun Park, Jung Hwan Choi, Kaushik Roy
    Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:520-521 [Conf]
  53. Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Mohammad Ashraful Alam, Kaushik Roy
    Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:780-785 [Conf]
  54. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
    Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:856-861 [Conf]
  55. Naran Sirisantana, Kaushik Roy
    Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11160-11161 [Conf]
  56. Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy
    Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:69-74 [Conf]
  57. Seung Hoon Choi, Kaushik Roy
    Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:365-369 [Conf]
  58. Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
    First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:314-315 [Conf]
  59. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:191-198 [Conf]
  60. Xiaodong Zhang, Kaushik Roy
    Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:148-0 [Conf]
  61. James R. Anderson, Siddharth Sheth, Kaushik Roy
    A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:234-244 [Conf]
  62. Kaushik Roy, Sudip Nag
    On Channel Architecture and Routability for FPGAs Under Faulty Conditions. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:361-372 [Conf]
  63. Kaushik Roy, Sharat Prasad
    Power Dissipation Driven FPGA Place and Route Under Delay Constraints. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:57-65 [Conf]
  64. Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy
    Energy recovery clocked dynamic logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:468-471 [Conf]
  65. Hendrawan Soeleman, Kaushik Roy
    Digital CMOS logic operation in the sub-threshold region. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:107-112 [Conf]
  66. Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy
    IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:243-248 [Conf]
  67. Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
    Deterministic Clock Gating for Microprocessor Power Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:113-0 [Conf]
  68. Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
    An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:147-158 [Conf]
  69. Kaushik Roy, Claire Tomlin
    A New Hybrid State Estimator for Systems with Limited Mode Changes. [Citation Graph (0, 0)][DBLP]
    HSCC, 2007, pp:487-500 [Conf]
  70. Amit Agarwal, Kunhyuk Kang, Kaushik Roy
    Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:736-741 [Conf]
  71. Zhanping Chen, Kaushik Roy, Tan-Li Chou
    Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:40-44 [Conf]
  72. Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
    Estimation of power sensitivity in sequential circuits with power macromodeling application. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:468-472 [Conf]
  73. Tan-Li Chou, Kaushik Roy
    Statistical estimation of sequential circuit activity. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:34-37 [Conf]
  74. Tan-Li Chou, Kaushik Roy, Sharat Prasad
    Estimation of circuit activity considering signal correlations and simultaneous switching. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:300-303 [Conf]
  75. Yonghee Im, Kaushik Roy
    CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:337-0 [Conf]
  76. Khurram Muhammad, Kaushik Roy
    A novel design methodology for high performance and low power digital filters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:80-83 [Conf]
  77. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Statistical design and optimization of SRAM cell for yield enhancement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:10-13 [Conf]
  78. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:487-490 [Conf]
  79. Arijit Raychowdhury, Kaushik Roy
    A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:237-240 [Conf]
  80. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-gate SOI devices for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:217-224 [Conf]
  81. Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
    Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:120-125 [Conf]
  82. Chuan-Yu Wang, Kaushik Roy
    COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:52-55 [Conf]
  83. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:208-213 [Conf]
  84. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Frequency Domain Analysis of Switching Noise on Power Supply Network. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:487-492 [Conf]
  85. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
    A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:406-411 [Conf]
  86. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
    On-chip interconnect modeling by wire duplication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:341-346 [Conf]
  87. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:619-624 [Conf]
  88. Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
    Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:583-586 [Conf]
  89. Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:206-214 [Conf]
  90. Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
    A Novel Low-Power Scan Design Technique Using Supply Gating. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:60-65 [Conf]
  91. Tan-Li Chou, Kaushik Roy
    Estimation of sequential circuit activity considering spatial and temporal correlations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:577-0 [Conf]
  92. Mark C. Johnson, Kaushik Roy
    Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:72-77 [Conf]
  93. Dongku Kang, Hunsoo Choo, Kaushik Roy
    Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:354-357 [Conf]
  94. Dongku Kang, Mark C. Johnson, Kaushik Roy
    Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:412-418 [Conf]
  95. Khurram Muhammad, Kaushik Roy
    On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:196-201 [Conf]
  96. Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy
    Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:230-235 [Conf]
  97. Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy
    A Soft Error Monitor Using Switching Current Detection. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:185-192 [Conf]
  98. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    A Feasibility Study of Subthreshold SRAM Across Technology Generations. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:417-424 [Conf]
  99. Kaushik Roy, Sudip Nag, Santanu Dutta
    Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:220-223 [Conf]
  100. Kaushik Roy, Sharat Prasad
    SYCLOP: Synthesis of CMOS Logic for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:464-467 [Conf]
  101. Naran Sirisantana, Liqiong Wei, Kaushik Roy
    High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:227-0 [Conf]
  102. Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
    Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:241-246 [Conf]
  103. Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
    Low Power Adder with Adaptive Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:103-106 [Conf]
  104. Chuan-Yu Wang, Kaushik Roy
    Control unit synthesis targeting low-power processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:454-0 [Conf]
  105. Chuan-Yu Wang, Kaushik Roy
    Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:746-751 [Conf]
  106. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:65-72 [Conf]
  107. Xiaowei Ding, Kaushik Roy
    A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2004, pp:- [Conf]
  108. Amit Agarwal, Bipul Chandra Paul, Kaushik Roy
    A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:149-154 [Conf]
  109. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    A Technique to Reduce Power and Test Application Time in BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:182-183 [Conf]
  110. Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
    Process Variation Tolerant Online Current Monitor for Robust Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:171-176 [Conf]
  111. Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
    A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:287-292 [Conf]
  112. Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
    Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:100-105 [Conf]
  113. Xiaodong Zhang, Kaushik Roy
    Power Reduction in Test-Per-Scan BIST. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:133-0 [Conf]
  114. Xiaodong Zhang, Kaushik Roy
    Power Constrained Test Scheduling with Low Power Weighted Random Testing. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:136- [Conf]
  115. Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:275-280 [Conf]
  116. Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:31-36 [Conf]
  117. Aditya Bansal, Kaushik Roy
    Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:1-4 [Conf]
  118. Yonghee Im, Kaushik Roy
    A logic-aware layout methodology to enhance the noise immunity of domino circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:637-640 [Conf]
  119. Santanu Dutta, Sudip Nag, Kaushik Roy
    ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:61-64 [Conf]
  120. Myeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy
    Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:709-712 [Conf]
  121. Kaushik Roy
    On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1623-1626 [Conf]
  122. Yongtao Wang, Kaushik Roy
    A novel low-complexity method for parallel multiplierless implementation of digital FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2020-2023 [Conf]
  123. Yongtao Wang, Kaushik Roy
    A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4963-4966 [Conf]
  124. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Power trends and performance characterization of 3-dimensional integration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:414-417 [Conf]
  125. Rui Wang, Kaushik Roy, Cheng-Kok Koh
    Short-circuit power analysis of an inverter driving an RLC load. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:886-889 [Conf]
  126. Kaushik Roy, Liqiong Wei, Zhanping Chen
    Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:366-370 [Conf]
  127. Hamid Mahmoodi-Meimand, Kaushik Roy
    Data-retention flip-flops for power-down applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:677-680 [Conf]
  128. Hamid Mahmoodi-Meimand, Kaushik Roy
    Dual-edge triggered level converting flip-flops. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:661-664 [Conf]
  129. Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
    Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:239-244 [Conf]
  130. Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
    Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:115-118 [Conf]
  131. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:229-234 [Conf]
  132. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
    Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:14-19 [Conf]
  133. Amit Agarwal, Kaushik Roy
    A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:18-21 [Conf]
  134. Hari Ananthan, Chris H. Kim, Kaushik Roy
    Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:8-13 [Conf]
  135. Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
    Energy recovery clocking scheme and flip-flops for ultra low-energy applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:54-59 [Conf]
  136. Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar
    An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:103-106 [Conf]
  137. Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
    Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:252-254 [Conf]
  138. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
    A forward body-biased low-leakage SRAM cache: device and architecture considerations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:6-9 [Conf]
  139. Hyung-il Kim, Kaushik Roy
    Ultra-low power DLMS adaptive filter for hearing aid applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:352-357 [Conf]
  140. Chris H. Kim, Kaushik Roy
    Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:251-254 [Conf]
  141. Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
    Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:8-13 [Conf]
  142. Saibal Mukhopadhyay, Kaushik Roy
    Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:172-175 [Conf]
  143. Cassondra Neau, Kaushik Roy
    Optimal body bias selection for leakage improvement and process compensation over different technology generations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:116-121 [Conf]
  144. Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
    High performance and low power FIR filter design based on sharing multiplication. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:295-300 [Conf]
  145. Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy
    Device optimization for ultra-low power digital sub-threshold operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:96-101 [Conf]
  146. Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy
    Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:267-270 [Conf]
  147. Hendrawan Soeleman, Kaushik Roy
    Ultra-low power digital subthreshold logic circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:94-96 [Conf]
  148. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
    Robust ultra-low power sub-threshold DTMOS logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:25-30 [Conf]
  149. Dinesh Somasekhar, Kaushik Roy
    LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:18-23 [Conf]
  150. Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
    Low-power carry-select adder using adaptive supply voltage based on input vector patterns. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:313-318 [Conf]
  151. Yibin Ye, Kaushik Roy, Georgios I. Stamoulis
    Quasi-static energy recovery logic and supply-clock generation circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:96-99 [Conf]
  152. Rongtian Zhang, Kaushik Roy, David B. Janes
    Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:213-218 [Conf]
  153. Ik Joon Chang, Jae-Joon Kim, Kaushik Roy
    Robust level converter design for sub-threshold logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:14-19 [Conf]
  154. Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy
    Analysis of super cut-off transistors for ultralow power digital logic circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:2-7 [Conf]
  155. Arijit Raychowdhury, Kaushik Roy
    A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:14-19 [Conf]
  156. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Decoupling capacitance allocation for power supply noise suppression. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:66-71 [Conf]
  157. Mark M. Budnik, Kaushik Roy
    Minimizing Ohmic Loss in Future Processor IR Events. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:650-658 [Conf]
  158. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
    Synthesis of Selectively Clocked Skewed Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:229-234 [Conf]
  159. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:389-394 [Conf]
  160. Hari Ananthan, Aditya Bansal, Kaushik Roy
    FinFET SRAM - Device and Circuit Design Considerations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:511-516 [Conf]
  161. Qikai Chen, Mesut Meterelliyoz, Kaushik Roy
    A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:243-248 [Conf]
  162. Zhanping Chen, Liqiong Wei, Kaushik Roy
    On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:181-188 [Conf]
  163. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
    Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:453-458 [Conf]
  164. Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy
    A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:358-363 [Conf]
  165. Kaushik Roy
    Low-Power Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:8- [Conf]
  166. Dongku Kang, Yiran Chen, Kaushik Roy
    Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:48-53 [Conf]
  167. Dongku Kang, Mark C. Johnson, Kaushik Roy
    Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:98-103 [Conf]
  168. Kee-Jong Kim, Chris H. Kim, Kaushik Roy
    TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:59-64 [Conf]
  169. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
    Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:410-415 [Conf]
  170. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:490-495 [Conf]
  171. Kaushik Roy, Ali Keshavarzi
    Design and Test of Low Voltage CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:7- [Conf]
  172. Xiaodong Zhang, Kaushik Roy
    Peak Power Reduction in Low Power BIST. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:425-432 [Conf]
  173. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:217-222 [Conf]
  174. Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy
    Fine-Grained Redundancy in Adders. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:317-321 [Conf]
  175. Tamer Cakici, Kee-Jong Kim, Kaushik Roy
    FinFET Based SRAM Design for Low Standby Power Applications. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:127-132 [Conf]
  176. Jaydeep P. Kulkarni, Kaushik Roy
    A High Performance, Scalable Multiplexed Keeper Technique. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:545-549 [Conf]
  177. Khurram Muhammad, Kaushik Roy
    A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:94-99 [Conf]
  178. Yonghee Im, Kaushik Roy
    LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:45-54 [Conf]
  179. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
    Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:146-155 [Conf]
  180. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1051-1059 [Conf]
  181. Kevin T. Kornegay, Kaushik Roy
    Integrated Test Solutions and Test Economics for MCMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:193-201 [Conf]
  182. Bipul Chandra Paul, Cassondra Neau, Kaushik Roy
    Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1269-1275 [Conf]
  183. Bipul Chandra Paul, Kaushik Roy
    Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:384-390 [Conf]
  184. Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy
    VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:19-28 [Conf]
  185. Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy
    Reducing set-associative cache energy via way-prediction and selective direct-mapping. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:54-65 [Conf]
  186. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Dynamic Noise Analysis with Capacitive and Inductive Coupling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:65-70 [Conf]
  187. Rajiv V. Joshi, Kaushik Roy
    Design of Deep Sub-Micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:15-16 [Conf]
  188. Mahesh Mehendale, Kaushik Roy
    Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:100-103 [Conf]
  189. Sudip Nag, H. K. Verma, Kaushik Roy
    VLSI Signal Processing in FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:609- [Conf]
  190. P. Patil, Tan-Li Chou, Kaushik Roy, R. Roy
    Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:179-184 [Conf]
  191. S. C. Prasad, Kaushik Roy
    Circuit optimization for minimisation of power consumption under delay constraint. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:305-309 [Conf]
  192. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    Modeling and Estimation of Leakage in Sub-90nm Devices. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:65-0 [Conf]
  193. Kaushik Roy, Khurram Muhammad
    Low Power VLSI Signal Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:12- [Conf]
  194. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-Gate SOI Devices for Low-Power and High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:445-452 [Conf]
  195. Kaushik Roy, R. K. Roy
    Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:2- [Conf]
  196. Kaushik Roy, Anand Raghunathan, Sujit Dey
    Low Power Design Methodologies for Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:609- [Conf]
  197. Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
    Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:174-178 [Conf]
  198. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
    Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:211-214 [Conf]
  199. Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik
    POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:416-422 [Conf]
  200. Shiyou Zhao, Kaushik Roy
    Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:168-0 [Conf]
  201. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:489-0 [Conf]
  202. Chuan-Yu Wang, Kaushik Roy
    Maximum power estimation for CMOS circuits using deterministic and statistic approaches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:364-369 [Conf]
  203. Liqiong Wei, Kaushik Roy, Vivek De
    Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:24-29 [Conf]
  204. Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    Process Variations and Process-Tolerant Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:699-704 [Conf]
  205. Qikai Chen, Arjun Guha, Kaushik Roy
    An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:615-620 [Conf]
  206. Swarup Bhunia, Kaushik Roy
    Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:302-310 [Conf]
  207. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:292-297 [Conf]
  208. Kaushik Roy, T. M. Mak, Kwang-Ting Cheng
    Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:313-318 [Conf]
  209. Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
    IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:2, pp:24-33 [Journal]
  210. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
    Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
  211. Khurram Muhammad, Kaushik Roy
    Fault Detection and Location Using IDD Waveform Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:42-49 [Journal]
  212. Kaushik Roy, Abhijit Chatterjee
    Guest Editors' Introduction: Low-Power VLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:6-7 [Journal]
  213. Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
    Test Consideration for Nanometer-Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:128-136 [Journal]
  214. Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy
    Enhancing Yield at the End of the Technology Roadmap. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:563-571 [Journal]
  215. Naran Sirisantana, Kaushik Roy
    Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:56-63 [Journal]
  216. Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou
    Estimating Circuit Activity in Combinational CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:112-119 [Journal]
  217. Kaushik Roy
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:63- [Journal]
  218. Bipul Chandra Paul, Amit Agarwal, Kaushik Roy
    Low-power design techniques for scaled technologies. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:64-89 [Journal]
  219. Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
    Leakage Current in Deep-Submicron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:575-600 [Journal]
  220. Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim
    Leakage Power Analysis and Reduction for Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:2, pp:68-80 [Journal]
  221. Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham
    Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:9, pp:1132-1145 [Journal]
  222. Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy
    GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:752-766 [Journal]
  223. Kaushik Roy, Sudip Nag
    On Routability for FPGAs under Faulty Conditions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:11, pp:1296-1305 [Journal]
  224. Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
    Estimation of power dissipation using a novel power macromodelingtechnique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1363-1369 [Journal]
  225. Tan-Li Chou, Kaushik Roy
    Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1257-1265 [Journal]
  226. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2427-2436 [Journal]
  227. Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
    Models and algorithms for bounds on leakage in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:714-725 [Journal]
  228. Kaushik Roy
    A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1695-1705 [Journal]
  229. Khurram Muhammad, Kaushik Roy
    A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:204-216 [Journal]
  230. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1486-1495 [Journal]
  231. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1859-1880 [Journal]
  232. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
    Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:363-381 [Journal]
  233. Jongsun Park, Khurram Muhammad, Kaushik Roy
    Efficient modeling of 1/falpha/ noise using multirate process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1247-1256 [Journal]
  234. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    A circuit-compatible model of ballistic carbon nanotube field-effect transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1411-1420 [Journal]
  235. Arijit Raychowdhury, Kaushik Roy
    Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:58-65 [Journal]
  236. Xiaodong Zhang, Wenlei Shan, Kaushik Roy
    Low-power weighted random pattern testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1389-1398 [Journal]
  237. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:81-92 [Journal]
  238. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
    On-chip interconnect modeling by wire duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1521-1532 [Journal]
  239. Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
    Synthesis of application-specific highly efficient multi-mode cores for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:168-188 [Journal]
  240. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
    Synthesis of skewed logic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:205-228 [Journal]
  241. Mark C. Johnson, Kaushik Roy
    Datapath scheduling with multiple supply voltages and level converters. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:3, pp:227-248 [Journal]
  242. S. C. Prasad, Kaushik Roy
    Transistor reordering for power minimization under delay constraint. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:2, pp:280-300 [Journal]
  243. Kunhyuk Kang, Bipul C. Paul, Kaushik Roy
    Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:848-879 [Journal]
  244. Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
    A process-tolerant cache architecture for improved yield in nanoscale technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:27-38 [Journal]
  245. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
    Low-power scan design using first-level supply gating. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:384-395 [Journal]
  246. Swarup Bhunia, Kaushik Roy
    A novel wavelet transform-based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:503-507 [Journal]
  247. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1286-1295 [Journal]
  248. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:75-85 [Journal]
  249. Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy
    Layout-driven architecture synthesis for high-speed digital filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:203-207 [Journal]
  250. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
    A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:349-357 [Journal]
  251. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
    Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1213-1224 [Journal]
  252. Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar
    DCG: deterministic clock-gating for low-power microprocessor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:245-254 [Journal]
  253. Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar
    Combined circuit and architectural level variable supply-voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:564-576 [Journal]
  254. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:183-192 [Journal]
  255. Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi
    Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1034-1039 [Journal]
  256. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
    A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:646-649 [Journal]
  257. Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:934-939 [Conf]
  258. Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Mohammad Ashraful Alam, Kaushik Roy
    Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:358-363 [Conf]
  259. Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
    High Performance and Low Power Electronics on Flexible Substrate. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:274-275 [Conf]
  260. Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy
    Process variation tolerant low power DCT architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:630-635 [Conf]
  261. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1532-1537 [Conf]
  262. Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy
    Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1550-1555 [Conf]
  263. Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy
    Tolerance to Small Delay Defects by Adaptive Clock Stretching. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:244-252 [Conf]
  264. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
    Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  265. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  266. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    Low-Power and testable circuit synthesis using Shannon decomposition. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
  267. Mark M. Budnik, Kaushik Roy
    A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1336-1346 [Journal]
  268. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
    Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:660-671 [Journal]
  269. Kaushik Roy, S. C. Prasad
    Circuit activity based logic synthesis for low power reliable operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:503-513 [Journal]
  270. Marc E. Levitt, Kaushik Roy, Jacob A. Abraham
    BiCMOS logic testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:241-248 [Journal]
  271. Kaushik Roy, Sudip Nag
    Automatic synthesis of FPGA channel architecture for routability and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:508-511 [Journal]
  272. Tan-Li Chou, Kaushik Roy
    Accurate power estimation of CMOS sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:3, pp:369-380 [Journal]
  273. Chuan-Yu Wang, Kaushik Roy
    Maximum power estimation for CMOS circuits using deterministic and statistical approaches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:134-140 [Journal]
  274. Zhanping Chen, Kaushik Roy, Tan-Li Chou
    Efficient statistical approach to estimate power considering uncertain properties of primary inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:484-492 [Journal]
  275. Dinesh Somasekhar, Kaushik Roy
    LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:573-577 [Journal]
  276. Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
    Design and optimization of dual-threshold circuits for low-voltage low-power applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:16-24 [Journal]
  277. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
    Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:717-723 [Journal]
  278. Zhanping Chen, Liqiong Wei, Kaushik Roy
    On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:718-725 [Journal]
  279. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
    Robust subthreshold logic for ultra-low power operation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:90-99 [Journal]
  280. Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, N. Vijaykumar
    Reducing leakage in a high-performance deep-submicron instruction cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:77-89 [Journal]
  281. Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
    Leakage control with efficient use of transistor stacks in single threshold CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:1-5 [Journal]
  282. Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
    Skewed CMOS: noise-tolerant high-performance low-power static circuit family. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:469-476 [Journal]
  283. Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes
    Vertically integrated SOI circuits for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:351-362 [Journal]
  284. Yonghee Im, Kaushik Roy
    O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:221-229 [Journal]
  285. Khurram Muhammad, Kaushik Roy
    Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:292-300 [Journal]
  286. Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy
    Gate leakage reduction for scaled devices using transistor stacking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:716-730 [Journal]
  287. C. H.-I. Kim, Hendrawan Soeleman, Kaushik Roy
    Ultra-low-power DLMS adaptive filter for hearing aid applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1058-1067 [Journal]
  288. Jongsun Park, Khurram Muhammad, Kaushik Roy
    High-performance FIR filter design based on sharing multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:244-253 [Journal]
  289. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:863-870 [Journal]
  290. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:243-255 [Journal]
  291. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:147-159 [Journal]
  292. Bipul C. Paul, Kaushik Roy
    Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:115-124 [Journal]

  293. An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. [Citation Graph (, )][DBLP]


  294. NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? [Citation Graph (, )][DBLP]


  295. Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. [Citation Graph (, )][DBLP]


  296. A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. [Citation Graph (, )][DBLP]


  297. Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations. [Citation Graph (, )][DBLP]


  298. Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. [Citation Graph (, )][DBLP]


  299. Process variation tolerant SRAM array for ultra low voltage applications. [Citation Graph (, )][DBLP]


  300. Device/circuit interactions at 22nm technology node. [Citation Graph (, )][DBLP]


  301. A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. [Citation Graph (, )][DBLP]


  302. Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. [Citation Graph (, )][DBLP]


  303. A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. [Citation Graph (, )][DBLP]


  304. Power-Aware Testing and Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP]


  305. Soft Errors: System Effects, Protection Techniques and Case Studies. [Citation Graph (, )][DBLP]


  306. Efficient power conversion for ultra low voltage micro scale energy transducers. [Citation Graph (, )][DBLP]


  307. Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. [Citation Graph (, )][DBLP]


  308. Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects. [Citation Graph (, )][DBLP]


  309. High level test generation using data flow descriptions. [Citation Graph (, )][DBLP]


  310. Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. [Citation Graph (, )][DBLP]


  311. The effect of process variation on device temperature in FinFET circuits. [Citation Graph (, )][DBLP]


  312. Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. [Citation Graph (, )][DBLP]


  313. Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. [Citation Graph (, )][DBLP]


  314. Indian Multi-Script Full Pin-code String Recognition for Postal Automation. [Citation Graph (, )][DBLP]


  315. Trilingual Script Separation of Handwritten Postal Document. [Citation Graph (, )][DBLP]


  316. Low-power process-variation tolerant arithmetic units using input-based elastic clocking. [Citation Graph (, )][DBLP]


  317. A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. [Citation Graph (, )][DBLP]


  318. Ultra low voltage CMOS. [Citation Graph (, )][DBLP]


  319. A low-power SRAM using bit-line charge-recycling technique. [Citation Graph (, )][DBLP]


  320. Low power design under parameter variations. [Citation Graph (, )][DBLP]


  321. A process variation aware low power synthesis methodology for fixed-point FIR filters. [Citation Graph (, )][DBLP]


  322. Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. [Citation Graph (, )][DBLP]


  323. Thermal analysis of 8-T SRAM for nano-scaled technologies. [Citation Graph (, )][DBLP]


  324. O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors. [Citation Graph (, )][DBLP]


  325. Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection. [Citation Graph (, )][DBLP]


  326. Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. [Citation Graph (, )][DBLP]


  327. HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs. [Citation Graph (, )][DBLP]


  328. Analysis and design of ultra low power thermoelectric energy harvesting systems. [Citation Graph (, )][DBLP]


  329. Impact of SoC power management techniques on verification and testing. [Citation Graph (, )][DBLP]


  330. PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. [Citation Graph (, )][DBLP]


  331. Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. [Citation Graph (, )][DBLP]


  332. Coping with Variations through System-Level Design. [Citation Graph (, )][DBLP]


  333. Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. [Citation Graph (, )][DBLP]


  334. Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. [Citation Graph (, )][DBLP]


  335. Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. [Citation Graph (, )][DBLP]


  336. Low power design under parameter variations. [Citation Graph (, )][DBLP]


  337. System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning. [Citation Graph (, )][DBLP]


  338. Reliability Implications of Bias-Temperature Instability in Digital ICs. [Citation Graph (, )][DBLP]


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