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Publications of Author

1. Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
   Making fast buffer insertion even faster via approximation techniques. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:13-18 [Conf]
   
2. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
   Register placement for low power clock network. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:588-593 [Conf]
   
3. Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
   A place and route aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:355-360 [Conf]
   
4. Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
   Skew scheduling and clock routing for improved tolerance to process variations. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:594-599 [Conf]
   
5. Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
   Timing-driven Steiner trees are (practically) free. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:389-392 [Conf]
   
6. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
   Fast algorithms for slew constrained minimum cost buffering. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:308-313 [Conf]
   
7. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
   Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:176-181 [Conf]
   
8. Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
   Path based buffer insertion. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:509-514 [Conf]
   
9. Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
   Integrated placement and skew optimization for rotary clocking. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:756-761 [Conf]
   
10. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:706-711 [Conf]
    
11. Cliff C. N. Sze, Ting-Chi Wang
    Optimal circuit clustering with variable interconnect delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:707-710 [Conf]
    
12. Cliff C. N. Sze, Ting-Chi Wang
    Multi-Level Circuit Clustering for Delay Minimization. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:227-232 [Conf]
    
13. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1140-1145 [Journal]
    
14. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
    Porosity-aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:517-526 [Journal]
    
15. Cliff C. N. Sze, Ting-Chi Wang
    Optimal circuit clustering for delay minimization under a more general delay model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:646-651 [Journal]
    
16. Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
    Multilevel circuit clustering for delay minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1073-1085 [Journal]
    
17. Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
    The nuts and bolts of physical synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:89-94 [Conf]
    
18. 
    The ISPD global routing benchmark suite. [Citation Graph (, )][DBLP]
    
    
19. 
    Ultra-fast interconnect driven cell cloning for minimizing critical path delay. [Citation Graph (, )][DBLP]