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Nikolaos Vassiliadis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dimitrios Soudris, Spiridon Nikolaidis, S. Siskos, Konstantinos Tatas, K. Siozios, G. Koutroumpezis, Nikolaos Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, Adonios Thanailakis
    AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:3-4 [Conf]
  2. Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
    An automated development framework for a RISC processor with reconfigurable instruction set extensions. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  3. Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, S. Siskos, Adonios Thanailakis
    FPGA Architecture Design and Toolset for Logic Implementation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:607-616 [Conf]
  4. Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis
    The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:593-602 [Conf]
  5. V. Kalenteridis, H. Pournara, K. Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, I. Pappas, G. Koutroumpezis, Spiridon Nikolaidis, S. Siskos, D. J. Soudris
    A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:6, pp:247-259 [Journal]
  6. Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
    The ARISE Reconfigurable Instruction Set Extensions Framework. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:153-160 [Conf]
  7. Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
    Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:217-229 [Conf]

  8. ARISE Machines: Extending Processors with Hybrid Accelerators. [Citation Graph (, )][DBLP]


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