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Poras T. Balsara: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
    Exploiting temporal idleness to reduce leakage power in programmable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:651-656 [Conf]
  2. N. S. Nagaraj, Poras T. Balsara, Cyrus Cantrell
    Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:141- [Conf]
  3. Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley
    Reconfigurable Array Media Processor (RAMP). [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:287-288 [Conf]
  4. Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara
    FPGA Architecture for Standby Power Management. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:181-188 [Conf]
  5. Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara
    Challenges in integrated CMOS transceivers for short distance wireless. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:45-50 [Conf]
  6. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
    PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:6-11 [Conf]
  7. Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara
    Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:243-248 [Conf]
  8. Sharat Prasad, Kamran Kiasaleh, Poras T. Balsara
    LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1998, pp:174-182 [Conf]
  9. Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara
    Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  10. Robert B. Staszewski, Chan Fernando, Poras T. Balsara
    Event-driven simulation and modeling of an RF oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:641-644 [Conf]
  11. Uming Ko, Poras T. Balsara, Ashwini K. Nanda
    Energy optimization of multi-level processor cache architectures. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:45-49 [Conf]
  12. Uming Ko, Anthony M. Hill, Poras T. Balsara
    Design techniques for high performance, energy efficient control logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:97-100 [Conf]
  13. Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara
    Leap frog multiplier. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:221-223 [Conf]
  14. Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara
    Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:262-267 [Conf]
  15. N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus Cantrell
    Benchmarks for Interconnect Parasitic Resistance and Capacitance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:163-0 [Conf]
  16. Robert B. Staszewski, Roman Staszewski, Poras T. Balsara
    VHDL Simulation and Modeling of an All-Digital RF Transmitter. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:233-238 [Conf]
  17. Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
    Exploring Logic Block Granularity in Leakage Tolerant FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:754-757 [Conf]
  18. N. S. Nagaraj, Poras T. Balsara, Cyrus Cantrell
    Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:141- [Conf]
  19. N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara
    Interconnect Modeling for Copper/Low-k Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:425-0 [Conf]
  20. N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus Cantrell
    The Impact of Inductance on Transients Affecting Gate Oxide Reliability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:709-713 [Conf]
  21. Nagaraj Ns, Poras T. Balsara, Cyrus Cantrell
    Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:365-370 [Conf]
  22. Nagaraj Ns, Poras T. Balsara, Cyrus Cantrell
    Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:6-11 [Conf]
  23. V. Ramakrishnan, Poras T. Balsara
    A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:197-202 [Conf]
  24. Ramaprasath Vilangudipitchai, Poras T. Balsara
    Power Switch Network Design for MTCMOS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:836-839 [Conf]
  25. Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara
    VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:836-841 [Conf]
  26. Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin
    Digit Serial Multipliers. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:11, n:2, pp:156-162 [Journal]
  27. Robert B. Staszewski, Roman Staszewski, John L. Wallberg, T. Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, K. Maggio, Poras T. Balsara
    SoC with an integrated DSP and a 2.4-GHz RF transmitter. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1253-1265 [Journal]
  28. Chitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara
    Effect of Word-length Precision on the Performance of MIMO Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2598-2601 [Conf]
  29. Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta
    A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3275-3278 [Conf]
  30. Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta
    A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3279-3282 [Conf]
  31. I. L. Syllaios, Poras T. Balsara, O. E. Eliezer
    A generalized signal reconstruction method for designing interpolation filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  32. Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara
    Generic Network Interfaces for Plug and Play NoC Based Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:287-298 [Conf]
  33. Uming Ko, Poras T. Balsara
    Short-circuit power driven gate sizing technique for reducing power dissipation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:450-455 [Journal]
  34. Uming Ko, Poras T. Balsara
    High-performance energy-efficient D-flip-flop circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:94-98 [Journal]
  35. M. Agarwala, Poras T. Balsara
    An architecture for a DSP field-programmable gate array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:136-141 [Journal]
  36. Uming Ko, Poras T. Balsara, Ashwini K. Nanda
    Energy optimization of multilevel cache architectures for RISC and CISC processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:299-308 [Journal]
  37. Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds
    High performance low power array multiplier using temporal tiling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:121-124 [Journal]
  38. Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara
    Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:42-51 [Journal]

  39. Reconfigurable CAM Architecture for Network Search Engines. [Citation Graph (, )][DBLP]


  40. Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels. [Citation Graph (, )][DBLP]


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