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Janusz Rajski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski
    Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:604-614 [Conf]
  2. Xijiang Lin, Janusz Rajski
    Propagation delay fault: a new fault model to test delay faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:178-183 [Conf]
  3. Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski
    Compactor Independent Direct Diagnosis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:204-209 [Conf]
  4. Janusz Rajski
    DFT for High-Quality Low Cost Manufacturing Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:3-0 [Conf]
  5. Janusz Rajski
    Embedded Test Technology - Brief History, Current Status, and Future Directions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:- [Conf]
  6. Xiaoliang Bai, Sujit Dey, Janusz Rajski
    Self-test methodology for at-speed test of crosstalk in chip interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:619-624 [Conf]
  7. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    A test pattern ordering algorithm for diagnosis with truncated fail data. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:399-404 [Conf]
  8. Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
    A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:625-631 [Conf]
  9. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
    On Test Set Preservation of Retimed Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:176-182 [Conf]
  10. Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Software Accelerated Functional Fault Simulation for Data-Path Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:333-338 [Conf]
  11. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Test response compactor with programmable selector. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1089-1094 [Conf]
  12. Stephen Pateras, Janusz Rajski
    Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:347-352 [Conf]
  13. Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
    STARBIST: Scan Autocorrelated Random Pattern Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:472-477 [Conf]
  14. Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy
    Finding a Common Fault Response for Diagnosis during Silicon Debug. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1116- [Conf]
  15. Janusz Rajski, Kan Thapar
    Nanometer Design: What are the Requirements for Manufacturing Test? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:930-937 [Conf]
  16. Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz
    Defect Aware Test Patterns. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:450-455 [Conf]
  17. Janusz Rajski
    Logic Diagnosis and Yield Learning. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:19- [Conf]
  18. Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
    Test pattern generation based on arithmetic operations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:117-124 [Conf]
  19. Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski
    Improving the Proportion of At-Speed Tests in Scan BIST. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:459-463 [Conf]
  20. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    On testable multipliers for fixed-width data path architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:541-547 [Conf]
  21. Janusz Rajski, Jerzy Tyszer, Babak Salimi
    On the Diagnostic Resolution of Signature Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:364-367 [Conf]
  22. Jagadeesh Vasudevamurthy, Janusz Rajski
    A Method for Concurrent Decomposition and Factorization of Boolean Expressions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:510-513 [Conf]
  23. Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
    Conflict driven techniques for improving deterministic test pattern generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:87-93 [Conf]
  24. Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer
    On Compacting Test Response Data Containing Unknown Values. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:855-862 [Conf]
  25. Janusz Rajski, Jerzy Tyszer
    Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:331-0 [Conf]
  26. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Multiple Fault Diagnosis Using n-Detection Tests. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:198-0 [Conf]
  27. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Diagnosis of Hold Time Defects. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:192-199 [Conf]
  28. Janusz Rajski, Jerzy Tyszer
    The detection of small size multiple faults by single fault test sets n programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1984, pp:417-425 [Conf]
  29. Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski
    Delay Fault Diagnosis for Non-Robust Test. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:463-472 [Conf]
  30. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Delay Fault Diagnosis Using Timing Information. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:485-490 [Conf]
  31. Vinod K. Agarwal, Janusz Rajski
    Testing Properties and Applications of Inverter-Free PLA's. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:500-507 [Conf]
  32. Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski
    Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1285-1294 [Conf]
  33. Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski
    Impact of Multiple-Detect Test Patterns on Product Quality. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1031-1040 [Conf]
  34. John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
    Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:258-267 [Conf]
  35. Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski
    On Multiple Fault Coverage and Aliasing Probability Measures. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:314-321 [Conf]
  36. Henry Cox, Janusz Rajski
    Stuck-Open and Transition Fault Testing in CMOS Complex Gates. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:688-694 [Conf]
  37. Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
    Realizing High Test Quality Goals with Smart Test Resource Usage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:525-533 [Conf]
  38. Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski
    Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:126-137 [Conf]
  39. Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie
    Testing of Glue Logic Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:700-711 [Conf]
  40. Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski
    Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:120-129 [Conf]
  41. Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
    Logic BIST for large industrial designs: real issues and case studies. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:358-367 [Conf]
  42. Mark Kassab, Janusz Rajski, Jerzy Tyszer
    Hierarchical Functional-Fault Simulation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:596-605 [Conf]
  43. Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
    On static test compaction and test pattern ordering for scan designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1088-1097 [Conf]
  44. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    Synthesis of pattern generators based on cellular automata with phase shifters. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:368-377 [Conf]
  45. Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski
    Fault Diagnosis in Designs with Convolutional Compactors. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:498-507 [Conf]
  46. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Parameterizable Testing Scheme for FIR Filters. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:694-703 [Conf]
  47. Stephen Pateras, Janusz Rajski
    Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:473-482 [Conf]
  48. Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
    Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1211-1220 [Conf]
  49. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:301-310 [Conf]
  50. Janusz Rajski
    Test Challenges of Nanometer Technology. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:13-22 [Conf]
  51. Janusz Rajski, Jerzy Tyszer
    Fault Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:894-902 [Conf]
  52. Janusz Rajski, Jerzy Tyszer
    Modular logic built-in self-test for IP cores. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:313-0 [Conf]
  53. Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
    Automated synthesis of large phase shifters for built-in self-test. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1047-1056 [Conf]
  54. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
    Convolutional Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:745-754 [Conf]
  55. Markus Robinson, Janusz Rajski
    An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:784-795 [Conf]
  56. Nagesh Tamarapalli, Janusz Rajski
    Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:649-658 [Conf]
  57. Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
    Scan-Encoded Test Pattern Generation for BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:548-556 [Conf]
  58. Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska
    STAR-ATPG: a high speed test pattern generator for large scan designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1021-1030 [Conf]
  59. Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
    An Efficient and Effective Methodology on the Multiple Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:329-338 [Conf]
  60. Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski
    Two-Dimensional Test Data Decompressor for Multiple Scan Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:186-194 [Conf]
  61. Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski
    Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:604-0 [Conf]
  62. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:419-424 [Conf]
  63. Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht
    Embedded Test for Low Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:21-23 [Conf]
  64. Janusz Rajski, Jerzy Tyszer, Sanjay Patel
    Built-In Self-Test for Systems on Silicon. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:609-610 [Conf]
  65. Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz
    On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:59-64 [Conf]
  66. Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    Low Shift and Capture Power Scan Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:793-798 [Conf]
  67. J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian
    Systems On Silicon: Design and Test Challenges. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:184-185 [Conf]
  68. J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski
    Innovations in Test Automation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:43-46 [Conf]
  69. J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
    Hardware-Software Co-Design for Test: It's the Last Straw! [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:506-507 [Conf]
  70. John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
    Enabling Embedded Memory Diagnosis via Test Response Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:292-298 [Conf]
  71. Xijiang Lin, Janusz Rajski
    The Impacts of Untestable Defects on Transition Fault Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:2-7 [Conf]
  72. Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Planar High Performance Ring Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:193-198 [Conf]
  73. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    High Speed Ring Generators and Compactors of Test Data. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:57-62 [Conf]
  74. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:377-388 [Conf]
  75. Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer
    Arithmetic built-in self test for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:132-139 [Conf]
  76. Fidel Muradali, Janusz Rajski
    A self-driven test structure for pseudorandom testing of non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:17-25 [Conf]
  77. Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer
    Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:236-245 [Conf]
  78. Wojciech Rajski, Janusz Rajski
    Modular Compactor of Test Responses. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:242-251 [Conf]
  79. Janusz Rajski, Jerzy Tyszer
    Synthesis of X-Tolerant Convolutional Compactors. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:114-119 [Conf]
  80. Janusz Rajski, Jerzy Tyszer
    Design of Phase Shifters for BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:218-224 [Conf]
  81. Marc Riedel, Janusz Rajski
    Fault coverage analysis of RAM test algorithms. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:227-234 [Conf]
  82. Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware
    Silicon Evaluation of Static Alternative Fault Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:265-270 [Conf]
  83. Nadime Zacharia, Janusz Rajski, Jerzy Tyszer
    Decompression of test data using variable-length seed LFSRs. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:426-433 [Conf]
  84. Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Low Power Embedded Deterministic Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:75-83 [Conf]
  85. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
    Scan Tests with Multiple Fault Activation Cycles for Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:343-348 [Conf]
  86. Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli
    High-Frequency, At-Speed Scan Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:17-25 [Journal]
  87. Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly
    Testability Implications of Performance-Driven Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:32-39 [Journal]
  88. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    2D Test Sequence Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:51-59 [Journal]
  89. Ashish Pancholy, Janusz Rajski, Larry J. McNaughton
    Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:1, pp:72-83 [Journal]
  90. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:58-66 [Journal]
  91. Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
    Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:939-949 [Journal]
  92. Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois
    Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:2, pp:223-233 [Journal]
  93. Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    High Performance Dense Ring Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:1, pp:83-87 [Journal]
  94. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Testing Schemes for FIR Filter Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:7, pp:674-688 [Journal]
  95. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Design of Testable Multipliers for Fixed-Width Data Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:7, pp:795-810 [Journal]
  96. Janusz Rajski, Jerzy Tyszer
    Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:6, pp:549-553 [Journal]
  97. Janusz Rajski, Jerzy Tyszer
    The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:81-85 [Journal]
  98. Janusz Rajski, Jerzy Tyszer
    Accumulator-Based Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:6, pp:643-650 [Journal]
  99. Janusz Rajski, Jerzy Tyszer
    Recursive Pseudoexhaustive Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:12, pp:1517-1521 [Journal]
  100. Janusz Rajski, Jerzy Tyszer
    On Linear Dependencies in Subspaces of LFSR-Generated Sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:10, pp:1212-1216 [Journal]
  101. Janusz Rajski, Jerzy Tyszer
    Diagnosis of Scan Cells in BIST Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:7, pp:724-731 [Journal]
  102. Janusz Rajski, Jerzy Tyszer, Nadime Zacharia
    Test Data Decompression for Multiple Scan Designs with Boundary Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1188-1200 [Journal]
  103. Henry Cox, Janusz Rajski
    A method of fault analysis for test generation and fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:813-833 [Journal]
  104. Henry Cox, Janusz Rajski
    On necessary and nonconflicting assignments in algorithmic test pattern generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:515-530 [Journal]
  105. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
    Behavior and testability preservation under the retiming transformation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:528-543 [Journal]
  106. Aiman H. El-Maleh, Janusz Rajski
    Delay-fault testability preservation of the concurrent decomposition and factorization transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:582-590 [Journal]
  107. Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski
    BIST of PCB interconnects using boundary-scan architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1278-1288 [Journal]
  108. Fadi Maamari, Janusz Rajski
    A method of fault simulation based on stem regions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:212-220 [Journal]
  109. Fadi Maamari, Janusz Rajski
    The dynamic reduction of fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:137-148 [Journal]
  110. Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
    A complexity analysis of sequential ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1409-1423 [Journal]
  111. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Cellular automata-based test pattern generators with phase shifters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:878-893 [Journal]
  112. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Ring generators - new devices for embedded test applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1306-1320 [Journal]
  113. Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer
    Arithmetic built-in self-test for DSP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1358-1369 [Journal]
  114. Janusz Rajski, Jerzy Tyszer
    On the diagnostic properties of linear feedback shift registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:10, pp:1316-1322 [Journal]
  115. Janusz Rajski, Jerzy Tyszer
    Test responses compaction in accumulators with rotate carry adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:4, pp:531-539 [Journal]
  116. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
    Embedded deterministic test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:776-792 [Journal]
  117. Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
    Automated synthesis of phase shifters for built-in self-testapplications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1175-1188 [Journal]
  118. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
    Finite memory test response compactors for embedded test applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:622-634 [Journal]
  119. Janusz Rajski, Jagadeesh Vasudevamurthy
    The testability-preserving concurrent decomposition and factorization of Boolean expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:778-793 [Journal]
  120. Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska
    Star test: the theory and its applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1052-1064 [Journal]
  121. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Delay-fault diagnosis using timing information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1315-1325 [Journal]
  122. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Analysis and methodology for multiple-fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:558-575 [Journal]
  123. Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
    Test Generation in the Presence of Timing Exceptions and Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:688-693 [Conf]
  124. Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
    New Test Data Decompressor for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:539-544 [Conf]
  125. Artur Pogiel, Janusz Rajski, Jerzy Tyszer
    Convolutional Compactors with Variable Polynomials. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:117-122 [Conf]
  126. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
    Enhancing Delay Fault Coverage through Low Power Segmented Scan. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:21-28 [Conf]
  127. Huaxing Tang, Sharma Manish, Janusz Rajski, Martin Keim, Brady Benware
    Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:145-150 [Conf]
  128. Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer
    Isolation of Failing Scan Cells through Convolutional Test Response Compaction. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:35-45 [Journal]

  129. N-distinguishing Tests for Enhanced Defect Diagnosis. [Citation Graph (, )][DBLP]


  130. A scalable method for the generation of small test sets. [Citation Graph (, )][DBLP]


  131. ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. [Citation Graph (, )][DBLP]


  132. Timing-Aware Multiple-Delay-Fault Diagnosis. [Citation Graph (, )][DBLP]


  133. High-Speed On-Chip Event Counters for Embedded Systems. [Citation Graph (, )][DBLP]


  134. Defect Aware to Power Conscious Tests - The New DFT Landscape. [Citation Graph (, )][DBLP]


  135. Diagnosis of failing scan cells through orthogonal response compaction. [Citation Graph (, )][DBLP]


  136. We Have Got Compression, What Next? [Citation Graph (, )][DBLP]


  137. X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. [Citation Graph (, )][DBLP]


  138. Scan-Based Tests with Low Switching Activity. [Citation Graph (, )][DBLP]


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