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Publications of Author

1. Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti
   Discovering the input assumptions in specification refinement coverage. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:13-18 [Conf]
   
2. Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra
   Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:1064-1069 [Conf]
   
3. Chunduri Rama Mohan, Partha Pratim Chakrabarti
   A new approach for factorizing FSM's. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:698-701 [Conf]
   
4. Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti
   SAT based solutions for consistency problems in formal property specifications for open systems. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:885-888 [Conf]
   
5. Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti
   Open computation tree logic with fairness. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:249-252 [Conf]
   
6. Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose
   Controlling State Explosion in Static Simulation by Selective Composition. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:226-231 [Conf]
   
7. Chunduri Rama Mohan, Partha Pratim Chakrabarti
   A New Approach to Synthesis of PLA-Based FSM's. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:373-378 [Conf]
   
8. Chunduri Rama Mohan, Partha Pratim Chakrabarti
   Combined optimization of area and testability during state assignment of PLA-based FSM's. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1995, pp:408-413 [Conf]
   
9. Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose
   Combining State Assignment with PLA Folding. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1993, pp:9-14 [Conf]
   
10. Prabir K. Biswas, Jayanta Mukherjee, B. N. Chatterji, Partha Pratim Chakrabarti
    Qualitative Description of Three-Dimensional Scenes. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1992, v:6, n:4, pp:651-672 [Journal]
    
11. Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti
    Model checking on timed-event structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:601-611 [Journal]
    
12. Chunduri Rama Mohan, Partha Pratim Chakrabarti
    EARTH: combined state assignment of PLA-based FSM's targeting area and testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:727-731 [Journal]
    
13. 
    A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. [Citation Graph (, )][DBLP]
    
    
14. 
    ERfair Scheduler with Processor Shutdown. [Citation Graph (, )][DBLP]
    
    
15. 
    Cohesive Coverage Management for Simulation and Formal Property Verification. [Citation Graph (, )][DBLP]
    
    
16. 
    New Approaches to Design and Control of Time Limited Search Algorithms. [Citation Graph (, )][DBLP]
    
    
17. 
    Inline Assertions - Embedding Formal Properties in a Test Bench. [Citation Graph (, )][DBLP]
    
    
18. 
    Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. [Citation Graph (, )][DBLP]
    
    
19. 
    Coverage Management with Inline Assertions and Formal Test Points. [Citation Graph (, )][DBLP]