Search the dblp DataBase

Publications of Author

1. Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong
   FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1999, pp:363-0 [Conf]
   
2. Wangning Long, Yu-Liang Wu, Jinian Bian
   IBAW: an implication-tree based alternative-wiring logic transformation algorithm. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:415-422 [Conf]
   
3. Qiang Wu, Jinian Bian, Hongxi Xue
   System-level architectural exploration using allocation-on-demand technique. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1296-1298 [Conf]
   
4. Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue
   Property Classification for Functional Verification Based. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:503- [Conf]
   
5. Jianzhou Zhao, Jinian Bian, Weimin Wu
   PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie. [Citation Graph (0, 0)][DBLP]
   COMPSAC, 2004, pp:108-113 [Conf]
   
6. Kun Tong, Jinian Bian, Haili Wang
   Universal data model platform: the data-centric evolution for system level codesign. [Citation Graph (0, 0)][DBLP]
   CSCWD, 2006, pp:1037-1042 [Conf]
   
7. Shujun Deng, Weimin Wu, Jinian Bian
   Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving. [Citation Graph (0, 0)][DBLP]
   CSCWD, 2006, pp:522-528 [Conf]
   
8. Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu
   AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design. [Citation Graph (0, 0)][DBLP]
   CSCWD, 2006, pp:324-329 [Conf]
   
9. Feng Lin, Haili Wang, Jinian Bian
   HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. [Citation Graph (0, 0)][DBLP]
   FPT, 2005, pp:305-306 [Conf]
   
10. Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
    An effective buffer planning algorithm for IP based fixed-outline SOC placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:564-569 [Conf]
    
11. Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu
    A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. [Citation Graph (0, 0)][DBLP]
    ICESS, 2005, pp:275-286 [Conf]
    
12. Haili Wang, Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang
    CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICESS, 2004, pp:74-80 [Conf]
    
13. Qiang Wu, Jinian Bian, Hongxi Xue
    A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICESS, 2004, pp:150-157 [Conf]
    
14. Ming Zhu, Jinian Bian, Weimin Wu
    Model Optimization Techniques in a Verification Platform for Classified Properties. [Citation Graph (0, 0)][DBLP]
    ICESS, 2004, pp:542-548 [Conf]
    
15. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
    A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6230-6233 [Conf]
    
16. Yunfeng Wang, Jinian Bian, Xianlong Hong
    Interconnect delay optimization via high level re-synthesis after floorplanning. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5641-5644 [Conf]
    
17. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng
    Integrating dynamic thermal via planning with 3D floorplanning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:178-185 [Conf]
    
18. Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai
    Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:279-284 [Conf]
    
19. Kang Zhao, Jinian Bian, Sheqin Dong
    A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. [Citation Graph (0, 0)][DBLP]
    JCIS, 2006, pp:- [Conf]
    
20. Zuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
    Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:325-345 [Journal]
    
21. Yawen Niu, Jinian Bian, Haili Wang, Kun Tong
    An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. [Citation Graph (0, 0)][DBLP]
    CSCWD (Selected Papers), 2006, pp:118-127 [Conf]
    
22. Shujun Deng, Weimin Wu, Jinian Bian
    Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. [Citation Graph (0, 0)][DBLP]
    CSCWD (Selected Papers), 2006, pp:297-307 [Conf]
    
23. Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao
    EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:588-593 [Conf]
    
24. 
    Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints. [Citation Graph (, )][DBLP]
    
    
25. 
    Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. [Citation Graph (, )][DBLP]
    
    
26. 
    Low power clock buffer planning methodology in F-D placement for large scale circuit design. [Citation Graph (, )][DBLP]
    
    
27. 
    A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. [Citation Graph (, )][DBLP]
    
    
28. 
    A Management System of Metropolis Energy Information. [Citation Graph (, )][DBLP]
    
    
29. 
    Cache miss reduction through hardware-assisted loop optimization. [Citation Graph (, )][DBLP]
    
    
30. 
    Random stimulus generation with self-tuning. [Citation Graph (, )][DBLP]
    
    
31. 
    Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs. [Citation Graph (, )][DBLP]
    
    
32. 
    iTuCoMe: HCDFG-based incremental tuning HW/SW co-design methodology for multi-level exploration. [Citation Graph (, )][DBLP]
    
    
33. 
    Behavioral level dual-vth design for reduced leakage power with thermal awareness. [Citation Graph (, )][DBLP]
    
    
34. 
    MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. [Citation Graph (, )][DBLP]
    
    
35. 
    HyMacs: hybrid memory access optimization based on custom-instruction scheduling. [Citation Graph (, )][DBLP]
    
    
36. 
    Wirelength-driven force-directed 3D FPGA placement. [Citation Graph (, )][DBLP]
    
    
37. 
    Bus via reduction based on floorplan revising. [Citation Graph (, )][DBLP]
    
    
38. 
    A novel fixed-outline floorplanner with zero deadspace for hierarchical design. [Citation Graph (, )][DBLP]
    
    
39. 
    Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. [Citation Graph (, )][DBLP]
    
    
40. 
    Cell shifting aware of wirelength and overlap. [Citation Graph (, )][DBLP]
    
    
41. 
    A low power clock network placement framework. [Citation Graph (, )][DBLP]
    
    
42. 
    High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization. [Citation Graph (, )][DBLP]
    
    
43. 
    From Software to Hardware - A Novel TLM Auto-Generating Method. [Citation Graph (, )][DBLP]
    
    
44. 
    A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. [Citation Graph (, )][DBLP]
    
    
45. 
    A cooperative universal data model platform for the data-centric electronic system-level design. [Citation Graph (, )][DBLP]