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Jianwen Zhu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rami Beidas, Jianwen Zhu
    Scalable interprocedural register allocation for high level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:511-516 [Conf]
  2. Fang Fang, Jianwen Zhu
    Automatic process migration of datapath hard IP libraries. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:887-892 [Conf]
  3. Dennis Wu, Jianwen Zhu
    BDD-based two variable sharing extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1031-1034 [Conf]
  4. Zhong Wang, Jianwen Zhu
    Piecewise quadratic waveform matching with successive chord iteration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:274-279 [Conf]
  5. Jianwen Zhu, Daniel Gajski
    Compiling SpecC for simulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:57-62 [Conf]
  6. Jianwen Zhu, Daniel Gajski
    A unified formal model of ISA and FSMD. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:121-125 [Conf]
  7. Maghsoud Abbaspour, Jianwen Zhu
    Retargetable binary utilities. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:331-336 [Conf]
  8. Wai Sum Mong, Jianwen Zhu
    A retargetable micro-architecture simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:752-757 [Conf]
  9. Jianwen Zhu
    Towards scalable flow and context sensitive pointer analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:831-836 [Conf]
  10. Bin Wu, Jianwen Zhu, Farid N. Najm
    An analytical approach for dynamic range estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:472-477 [Conf]
  11. Bin Wu, Jianwen Zhu, Farid N. Najm
    A non-parametric approach for dynamic range estimation of nonlinear systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:841-844 [Conf]
  12. Jianwen Zhu, Daniel Gajski
    Soft Scheduling in High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:219-224 [Conf]
  13. Zhong Wang, Jianwen Zhu
    Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11026-11031 [Conf]
  14. Jianwen Zhu
    Static memory allocation by pointer analysis and coloring. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:785-790 [Conf]
  15. Jianwen Zhu, Daniel Gajski
    OpenJ: An Extensible System Level Design Language. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:480-484 [Conf]
  16. Jianwen Zhu, Wai Sum Mong
    Specification of Non-Functional Intellectual Property Components. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10456-10461 [Conf]
  17. Khushwinder Jasrotia, Jianwen Zhu
    Hardware Implementation of a Memory Allocator. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:355-358 [Conf]
  18. Rami Beidas, Jianwen Zhu
    A queuing-theoretic performance model for context-flow system-on-chip platforms. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:21-26 [Conf]
  19. Rami Beidas, Jianwen Zhu
    Performance Efficiency of Context-Flow System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:356-362 [Conf]
  20. Massimo Poncino, Jianwen Zhu
    DynamoSim: a trace-based dynamically compiled instruction set simulator. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:131-136 [Conf]
  21. Jianwen Zhu
    Symbolic pointer analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:150-157 [Conf]
  22. Bin Wu, Jianwen Zhu, Farid N. Najm
    Dynamic range estimation for nonlinear systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:660-667 [Conf]
  23. Jianwen Zhu, Edward S. Rogers Sr.
    Color Permutation: An Iterative Algorithm for Memory Packing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:380-383 [Conf]
  24. Daniel Gajski, Rainer Dömer, Jianwen Zhu
    IP-Centric Methodology and Specification Language. [Citation Graph (0, 0)][DBLP]
    DIPES, 1998, pp:3-22 [Conf]
  25. Fang Fang, Jianwen Zhu
    Calligrapher: A New Layout Migration Engine Based on Geometric Closeness. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:25-30 [Conf]
  26. Khushwinder Jasrotia, Jianwen Zhu
    Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:425-430 [Conf]
  27. Qianying Tang, Jianwen Zhu
    Two-Dimensional Layout Migration by Soft Constraint Satisfaction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:35-39 [Conf]
  28. Jianwen Zhu, Silvian Calman
    Symbolic pointer analysis revisited. [Citation Graph (0, 0)][DBLP]
    PLDI, 2004, pp:145-157 [Conf]
  29. Bin Wu, Jianwen Zhu, Farid N. Najm
    Dynamic-range estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1618-1636 [Journal]
  30. Jianwen Zhu, Silvian Calman
    Context sensitive symbolic pointer analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:516-531 [Journal]
  31. Jianwen Zhu, Fang Fang, Qianying Tang
    Calligrapher: a new layout-migration engine for hard intellectual property libraries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1347-1361 [Journal]
  32. Jianwen Zhu, Daniel D. Gajski
    An ultra-fast instruction set simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:363-373 [Journal]

  33. BddCut: Towards Scalable Symbolic Cut Enumeration. [Citation Graph (, )][DBLP]


  34. Towards automated ECOs in FPGAs. [Citation Graph (, )][DBLP]


  35. A 1 cycle-per-byte XML parsing accelerator. [Citation Graph (, )][DBLP]


  36. Towards scalable placement for FPGAs. [Citation Graph (, )][DBLP]


  37. Delay driven AIG restructuring using slack budget management. [Citation Graph (, )][DBLP]


  38. Interprocedural induction variable analysis based on interprocedural SSA form IR. [Citation Graph (, )][DBLP]


  39. Increasing the Scope and Resolution of Interprocedural Static Single Assignment. [Citation Graph (, )][DBLP]


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