The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Dhiraj K. Pradhan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
    Location Management in Distributed Mobile Environments. [Citation Graph (2, 6)][DBLP]
    PDIS, 1994, pp:81-88 [Conf]
  2. Nicholas S. Bowen, Dhiraj K. Pradhan
    Processor- and Memory-Based Checkpoint and Rollback Recovery. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:2, pp:22-31 [Journal]
  3. Subhasis Bhattacharjee, Dhiraj K. Pradhan
    LPRAM: a low power DRAM with testability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:390-393 [Conf]
  4. Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan
    Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:414-419 [Conf]
  5. Abusaleh M. Jabir, Dhiraj K. Pradhan
    MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1388-1389 [Conf]
  6. Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
    Reuse-based test access and integrated test scheduling for network-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:303-308 [Conf]
  7. Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty
    EBIST: A Novel Test Generator with Built-In Fault Detection Capability. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10224-10229 [Conf]
  8. Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
    Signal Transition Graph Transformations for Initializability. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:670- [Conf]
  9. Nicholas S. Bowen, Dhiraj K. Pradhan
    Program Fault Tolerance Based on Memory Access Behavior. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:426-435 [Conf]
  10. Dhiraj K. Pradhan, P. Krishna, Nitin H. Vaidya
    Recoverable Mobile Environment: Design and Trade-Off Analysis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:16-25 [Conf]
  11. Dhiraj K. Pradhan, Nitin H. Vaidya
    Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:186-195 [Conf]
  12. Nitin H. Vaidya, Dhiraj K. Pradhan
    System Level Diagnosis: Combining Detection and Location. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:488-495 [Conf]
  13. Dhiraj K. Pradhan, Debendra Das Sharma, Nitin H. Vaidya
    Roll-Forward Checkpointing Schemes. [Citation Graph (0, 0)][DBLP]
    Hardware and Software Architectures for Fault Tolerance, 1993, pp:95-116 [Conf]
  14. Wanlin Cao, Dhiraj K. Pradhan
    Sequential redundancy identification using recursive learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:56-62 [Conf]
  15. Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
    LOT: logic optimization with testability-new transformations using recursive learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:318-325 [Conf]
  16. Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee
    Buffer assignment for data driven architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:665-668 [Conf]
  17. Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee
    VERILAT: verification using logic augmentation and transformations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:88-95 [Conf]
  18. Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew
    An efficient technique for synthesis and optimization of polynomials in GF(2m). [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:151-157 [Conf]
  19. Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
    Initialization Isuues in the Synthesis of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:447-452 [Conf]
  20. Jayashree Saxena, Dhiraj K. Pradhan
    Desgin for Testability of Asynchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:518-522 [Conf]
  21. Bikram S. Bakshi, P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
    Improving Performance of TCP over Wireless Networks. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1997, pp:0-0 [Conf]
  22. Dhiraj K. Pradhan
    On a Class of Fault-Tolerant Multiprocessor Network Architectures. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1982, pp:302-311 [Conf]
  23. Nitin H. Vaidya, Dhiraj K. Pradhan
    Degradable Agreement in the Presence of Byzantine Faults. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1993, pp:237-244 [Conf]
  24. P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
    Recovery in Multicomputers with Finite Error Detection Latency. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:206-210 [Conf]
  25. Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan
    Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:326-330 [Conf]
  26. Debendra Das Sharma, G. D. Holland, Dhiraj K. Pradhan
    Subcube Level Time-Sharing in Hypercube Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:134-142 [Conf]
  27. Debendra Das Sharma, Dhiraj K. Pradhan
    Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:118-127 [Conf]
  28. Debendra Das Sharma, Dhiraj K. Pradhan
    Job Scheduling in Mesh Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:251-258 [Conf]
  29. Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch
    Modified Tree Structure for Location Management in Mobile Environments. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1995, pp:530-537 [Conf]
  30. Dhiraj K. Pradhan
    Logic Insertion to Speed-Up Logic Verification: A Recent Development. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:61-64 [Conf]
  31. Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir
    A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:221-226 [Conf]
  32. Elango Ganesan, Dhiraj K. Pradhan
    Optimal Broadcasting in Binary de Bruijn Networks and Hyper-de Bruijn Networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:655-660 [Conf]
  33. Yeong-Chang Maa, Dhiraj K. Pradhan, Dominique Thiébaut
    A Hierarchical Directory Scheme for Large-Scale Cache-Coherent Multipmcessors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:43-46 [Conf]
  34. Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
    Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:224-231 [Conf]
  35. Maheswara R. Samatham, Dhiraj K. Pradhan
    The de Bruijn Multiprocessor Network: A Versatile Sorting Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:360-367 [Conf]
  36. Elango Ganesan, Dhiraj K. Pradhan
    Wormhole routing in de Bruijn networks and hyper-de Bruijn networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:870-873 [Conf]
  37. Barun K. Kar, Khadem M. Yusuf, Dhiraj K. Pradhan
    Bit-Serial Generalized Median Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:85-88 [Conf]
  38. Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz
    Gate-level synthesis for low-power using new transformations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:297-300 [Conf]
  39. S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan
    Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:807-813 [Conf]
  40. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:380-385 [Conf]
  41. Sandeep K. Gupta, Dhiraj K. Pradhan
    A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:329-342 [Conf]
  42. Sandeep K. Gupta, Dhiraj K. Pradhan
    Can Concurrent Checkers Help BIST? [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:140-150 [Conf]
  43. Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan
    Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:828-839 [Conf]
  44. Wolfgang Kunz, Dhiraj K. Pradhan
    Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:816-825 [Conf]
  45. Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan
    Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1369-1378 [Conf]
  46. Dhiraj K. Pradhan, Mitrajit Chatterjee
    GLFSR - A New Test Pattern Generator for Built-In Self-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:481-490 [Conf]
  47. Dhiraj K. Pradhan, Nirmala R. Kamath
    RTRAM: Reconfigurable and Testable Multi-Bit RAM Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:263-278 [Conf]
  48. Jayashree Saxena, Dhiraj K. Pradhan
    A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:724-733 [Conf]
  49. Kyushik Son, Dhiraj K. Pradhan
    Completely Self-Checking Checkers in PLAs. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:231-240 [Conf]
  50. Bikram S. Bakshi, P. Krishna, Dhiraj K. Pradhan, Nitin H. Vaidya
    Providing Seamless Communication in Mobile Wireless Networks. [Citation Graph (0, 0)][DBLP]
    LCN, 1996, pp:535-543 [Conf]
  51. P. Krishna, Mainak Chatterjee, Nitin H. Vaidya, Dhiraj K. Pradhan
    A Cluster-based Approach for Routing in Ad-Hoc Networks. [Citation Graph (0, 0)][DBLP]
    Symposium on Mobile and Location-Independent Computing, 1995, pp:1-10 [Conf]
  52. Sathiamoorthy Subbarayan, Dhiraj K. Pradhan
    NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances. [Citation Graph (0, 0)][DBLP]
    SAT, 2004, pp:- [Conf]
  53. Sathiamoorthy Subbarayan, Dhiraj K. Pradhan
    NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances. [Citation Graph (0, 0)][DBLP]
    SAT (Selected Papers, 2004, pp:276-291 [Conf]
  54. Nicholas S. Bowen, Dhiraj K. Pradhan
    A virtual memory translation mechanism to support checkpoint and rollback recovery. [Citation Graph (0, 0)][DBLP]
    SC, 1991, pp:890-899 [Conf]
  55. Barun K. Kar, Dhiraj K. Pradhan
    Scalability of Binary deBruijn Networks. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:796-799 [Conf]
  56. Debendra Das Sharma, Dhiraj K. Pradhan
    A Novel Approach for Subcube Allocation in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1992, pp:336-345 [Conf]
  57. Debendra Das Sharma, Dhiraj K. Pradhan
    A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:682-689 [Conf]
  58. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
    Synthesis of Initializable Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:383-388 [Conf]
  59. Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea
    Recent Advances in Verification, Equivalence Checking and SAT-Solvers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:14- [Conf]
  60. H. Rahaman, Jimson Mathew, Dhiraj K. Pradhan
    Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:479-484 [Conf]
  61. Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
    ATPG for Design Errors-Is It Possible? [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:283-285 [Conf]
  62. Mitrajit Chatterjee, Dhiraj K. Pradhan
    A novel pattern generator for near-perfect fault-coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:417-425 [Conf]
  63. Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan
    Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:46-51 [Conf]
  64. H. Rahaman, Jimson Mathew, B. K. Sikdar, Dhiraj K. Pradhan
    Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:422-430 [Conf]
  65. Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch
    Modified tree structure for location management in mobile environments. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1996, v:19, n:4, pp:335-345 [Journal]
  66. P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
    Static and adaptive location management in mobile wireless networks. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1996, v:19, n:4, pp:321-334 [Journal]
  67. Jeffrey A. Clark, Dhiraj K. Pradhan
    Fault Injection: A Method for Validating Computer-System Dependability. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:6, pp:47-56 [Journal]
  68. Eiji Fujiwara, Dhiraj K. Pradhan
    Error-Control Coding in Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:7, pp:63-72 [Journal]
  69. L. C. Chang, Dhiraj K. Pradhan
    A graph-structural approach for the generalization of data management systems. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1977, v:12, n:1, pp:1-18 [Journal]
  70. Debendra Das Sharma, Dhiraj K. Pradhan
    Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:36, n:2, pp:106-118 [Journal]
  71. Bella Bose, Dhiraj K. Pradhan
    Optimal Unidirectional Error Detecting/Correcting Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:6, pp:564-568 [Journal]
  72. Nicholas S. Bowen, Dhiraj K. Pradhan
    Virtual Checkpoints: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:516-525 [Journal]
  73. Nicholas S. Bowen, Dhiraj K. Pradhan
    A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:408-418 [Journal]
  74. Nicholas S. Bowen, Dhiraj K. Pradhan
    The Effect of Program Behavior on Fault Observability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:868-880 [Journal]
  75. Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan
    Buffer Assignment Algorithms on Data Driven ASICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:1, pp:16-32 [Journal]
  76. Mitrajit Chatterjee, Dhiraj K. Pradhan
    A BIST Pattern Generator Design for Near-Perfect Fault Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:12, pp:1543-1558 [Journal]
  77. Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
    Design and Analysis of a Gracefully Degrading Interleaved Memory System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:1, pp:63-71 [Journal]
  78. Sandeep K. Gupta, Dhiraj K. Pradhan
    Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:63-73 [Journal]
  79. M. Y. Hsiao, Arvind M. Patel, Dhiraj K. Pradhan
    Store Address Generator with On-Line Fault-Detection Capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:11, pp:1144-1151 [Journal]
  80. Najmi T. Jarwala, Dhiraj K. Pradhan
    TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:10, pp:1235-1250 [Journal]
  81. Kolar L. Kodandapani, Dhiraj K. Pradhan
    Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:1, pp:55-59 [Journal]
  82. Israel Koren, Dhiraj K. Pradhan
    Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:3, pp:344-355 [Journal]
  83. Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan
    Modeling Live and Dead Lines in Cache Memory Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:1, pp:1-14 [Journal]
  84. Fred J. Meyer, Dhiraj K. Pradhan
    Flip-Trees: Fault-Tolerant Graphs with Wide Containers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:4, pp:472-478 [Journal]
  85. Fred J. Meyer, Dhiraj K. Pradhan
    Dynamic Testing Strategy for Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:3, pp:356-365 [Journal]
  86. Fred J. Meyer, Dhiraj K. Pradhan
    Modeling Defect Spatial Distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:4, pp:538-546 [Journal]
  87. Dhiraj K. Pradhan
    Fault-Tolerant Asynchronous Networks Using Read-Only Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:7, pp:674-679 [Journal]
  88. Dhiraj K. Pradhan
    Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:2, pp:181-187 [Journal]
  89. Dhiraj K. Pradhan
    A Theory of Galois Switching Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:3, pp:239-248 [Journal]
  90. Dhiraj K. Pradhan
    Asynchronous State Assignments with Unateness Properties and Fault-Secure Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:5, pp:396-404 [Journal]
  91. Dhiraj K. Pradhan
    A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:471-481 [Journal]
  92. Dhiraj K. Pradhan
    Sequential Network Design Using Extra Inputs for Fault Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:3, pp:319-323 [Journal]
  93. Dhiraj K. Pradhan
    Dynamically Restructurable Fault-Tolerant Processor Network Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:5, pp:434-447 [Journal]
  94. Dhiraj K. Pradhan, Sandeep K. Gupta
    A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:743-763 [Journal]
  95. Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky
    Aliasing Probability for Multiple Input Signature Analyzer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:586-591 [Journal]
  96. Dhiraj K. Pradhan, Kolar L. Kodandapani
    A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:9, pp:777-791 [Journal]
  97. Dhiraj K. Pradhan, Arvind M. Patel
    Reed-Muller Like Canonic Forms for Multivalued Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:2, pp:206-210 [Journal]
  98. Dhiraj K. Pradhan, Sudhakar M. Reddy
    Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:9, pp:945-949 [Journal]
  99. Dhiraj K. Pradhan, Sudhakar M. Reddy
    A Fault-Tolerant Communication Architecture for Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:9, pp:863-870 [Journal]
  100. Dhiraj K. Pradhan, Nitin H. Vaidya
    Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:10, pp:1163-1174 [Journal]
  101. Dhiraj K. Pradhan, Nitin H. Vaidya
    Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:3, pp:372-378 [Journal]
  102. Maheswara R. Samatham, Dhiraj K. Pradhan
    The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:4, pp:567-581 [Journal]
  103. Nitin H. Vaidya, Dhiraj K. Pradhan
    Fault-Tolerant Design Strategies for High Reliability and Safety. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:10, pp:1195-1206 [Journal]
  104. Nitin H. Vaidya, Dhiraj K. Pradhan
    Safe System Level Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:3, pp:367-370 [Journal]
  105. Subhasis Bhattacharjee, Dhiraj K. Pradhan
    LPRAM: a novel low-power high-performance RAM design with testability and scalability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:637-651 [Journal]
  106. Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
    LOT: Logic Optimization with Testability. New transformations for logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:386-399 [Journal]
  107. Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy
    A novel framework for logic verification in a synthesis environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:20-32 [Journal]
  108. Wolfgang Kunz, Dhiraj K. Pradhan
    Accelerated dynamic learning for test pattern generation in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:684-694 [Journal]
  109. Wolfgang Kunz, Dhiraj K. Pradhan
    Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1143-1158 [Journal]
  110. Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan
    VERILAT: verification using logic augmentation and transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1041-1051 [Journal]
  111. Dhiraj K. Pradhan, Mitrajit Chatterjee
    GLFSR-a new test pattern generator for built-in-self-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:238-247 [Journal]
  112. Dhiraj K. Pradhan, Chunsheng Liu
    EBIST: a novel test generator with built-in fault detection capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1457-1466 [Journal]
  113. Dhiraj K. Pradhan, Jayashree Saxena
    A novel scheme to reduce test application time in circuits with full scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1577-1586 [Journal]
  114. Nitin H. Vaidya, Dhiraj K. Pradhan
    A new class of bit- and byte-error control codes. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Theory, 1992, v:38, n:5, pp:1617-0 [Journal]
  115. Elango Ganesan, Dhiraj K. Pradhan
    The Hyper-deBruijn Networks: Scalable Versatile Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:9, pp:962-978 [Journal]
  116. Fred J. Meyer, Dhiraj K. Pradhan
    Consensus With Dual Failure Modes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1991, v:2, n:2, pp:214-222 [Journal]
  117. Debendra Das Sharma, Dhiraj K. Pradhan
    Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:10, pp:1108-1122 [Journal]
  118. Debendra Das Sharma, Dhiraj K. Pradhan
    Job Scheduling in Mesh Multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:1, pp:57-70 [Journal]
  119. Costas Argyrides, Dhiraj K. Pradhan
    Highly Reliable Power Aware Memory Design. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:189-190 [Conf]
  120. Jimson Mathew, H. Rahaman, Dhiraj K. Pradhan
    Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:207-208 [Conf]
  121. Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
    Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  122. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3675-3678 [Conf]
  123. Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
    Multiple Upsets Tolerance in SRAM Memory. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:365-368 [Conf]
  124. R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan
    On the Hardware Reduction of z-Datapath of Vectoring CORDIC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3002-3005 [Conf]
  125. Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
    CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3696-3699 [Conf]
  126. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:141-144 [Conf]
  127. Abusaleh M. Jabir, Dhiraj K. Pradhan
    A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:8, pp:1119-1132 [Journal]
  128. Abusaleh M. Jabir, Dhiraj K. Pradhan, T. L. Rajaprabhu, A. K. Singh
    A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:8, pp:1133-1145 [Journal]
  129. D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan
    Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:546-558 [Journal]
  130. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
    Synthesis of initializable asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:254-263 [Journal]

  131. Single Event Upset Detection and Correction. [Citation Graph (, )][DBLP]


  132. De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. [Citation Graph (, )][DBLP]


  133. Single ended 6T SRAM with isolated read-port for low-power embedded systems. [Citation Graph (, )][DBLP]


  134. Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. [Citation Graph (, )][DBLP]


  135. A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. [Citation Graph (, )][DBLP]


  136. The hyper-deBruijn multiprocessor networks. [Citation Graph (, )][DBLP]


  137. Fault Tolerant Reversible Finite Field Arithmetic Circuits. [Citation Graph (, )][DBLP]


  138. Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. [Citation Graph (, )][DBLP]


  139. Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. [Citation Graph (, )][DBLP]


  140. A fast error correction technique for matrix multiplication algorithms. [Citation Graph (, )][DBLP]


  141. C-testable S-box implementation for secure advanced encryption standard. [Citation Graph (, )][DBLP]


  142. A nano-CMOS process variation induced read failure tolerant SRAM cell. [Citation Graph (, )][DBLP]


  143. Fault tolerant bit parallel finite field multipliers using LDPC codes. [Citation Graph (, )][DBLP]


  144. Increasing memory yield in future technologies through innovative design. [Citation Graph (, )][DBLP]


  145. A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. [Citation Graph (, )][DBLP]


  146. On the design of different concurrent EDC schemes for S-Box and GF(p). [Citation Graph (, )][DBLP]


  147. P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. [Citation Graph (, )][DBLP]


  148. Layout-aware Illinois Scan design for high fault coverage coverage. [Citation Graph (, )][DBLP]


  149. Fault diagnosis in multi layered De Bruijn based architectures for sensor networks. [Citation Graph (, )][DBLP]


  150. Area Reliability Trade-Off in Improved Reed Muller Coding. [Citation Graph (, )][DBLP]


  151. A soft error robust and power aware memory design. [Citation Graph (, )][DBLP]


  152. Reliability aware yield improvement technique for nanotechnology based circuits. [Citation Graph (, )][DBLP]


  153. BDG-torus union graph-an efficient algorithmically specializedparallel interconnect. [Citation Graph (, )][DBLP]


  154. Design of Reversible Finite Field Arithmetic Circuits with Error Detection. [Citation Graph (, )][DBLP]


  155. A Galois Field Based Logic Synthesis Approach with Testability. [Citation Graph (, )][DBLP]


  156. Single Error Correcting Finite Field Multipliers Over GF(2m). [Citation Graph (, )][DBLP]


  157. Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. [Citation Graph (, )][DBLP]


  158. A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. [Citation Graph (, )][DBLP]


  159. Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. [Citation Graph (, )][DBLP]


  160. On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. [Citation Graph (, )][DBLP]


  161. A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. [Citation Graph (, )][DBLP]


  162. Failure analysis for ultra low power nano-CMOS SRAM under process variations. [Citation Graph (, )][DBLP]


  163. Pseudo parallel architecture for AES with error correction. [Citation Graph (, )][DBLP]


Search in 0.009secs, Finished in 0.768secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002