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Author:
Krishnendu Chakrabarty: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty
    Synthesis of single-output space compactors with application to scan-based IP cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:496-502 [Conf]
  2. Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
    Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:59-64 [Conf]
  3. Vishnu Swaminathan, Krishnendu Chakrabarty
    Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:251- [Conf]
  4. Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty
    Robust Space Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:254-259 [Conf]
  5. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:320-0 [Conf]
  6. Tao Xu, Krishnendu Chakrabarty
    Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:112-117 [Conf]
  7. Krishnendu Chakrabarty, Fei Su
    System-level design automation tools for digital microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:201-206 [Conf]
  8. Vishnu Swaminathan, Krishnendu Chakrabarty
    Pruning-based energy-optimal device scheduling for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:175-180 [Conf]
  9. Vishnu Swaminathan, Krishnendu Chakrabarty, S. Sitharama Iyengar
    Dynamic I/O power management for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:237-242 [Conf]
  10. Anshuman Chandra, Krishnendu Chakrabarty
    Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:166-169 [Conf]
  11. Anshuman Chandra, Krishnendu Chakrabarty
    Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:673-678 [Conf]
  12. Krishnendu Chakrabarty
    Design of system-on-a-chip test access architectures under place-and-route and power constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:432-437 [Conf]
  13. Krishnendu Chakrabarty, John P. Hayes
    DFBT: A Design-for-Testability Method Based on Balance Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:351-357 [Conf]
  14. William L. Hwang, Fei Su, Krishnendu Chakrabarty
    Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:925-930 [Conf]
  15. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:685-690 [Conf]
  16. Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
    Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:738-743 [Conf]
  17. Fei Su, Krishnendu Chakrabarty
    Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:825-830 [Conf]
  18. Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
    Multi-frequency wrapper design and optimization for embedded cores under average power constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:123-128 [Conf]
  19. Ying Zhang, Robert P. Dick, Krishnendu Chakrabarty
    Energy-aware deterministic fault tolerance in distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:550-555 [Conf]
  20. Lei Li, Krishnendu Chakrabarty
    Hybrid BIST Based on Repeating Sequences and Cluster Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1142-1147 [Conf]
  21. Fei Su, Krishnendu Chakrabarty
    Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1202-1207 [Conf]
  22. Anshuman Chandra, Krishnendu Chakrabarty
    Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:145-149 [Conf]
  23. Anshuman Chandra, Krishnendu Chakrabarty
    Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:598-603 [Conf]
  24. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient Wrapper/TAM Co-Optimization for Large SOCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:491-498 [Conf]
  25. Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty
    A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11188-11190 [Conf]
  26. Chunsheng Liu, Krishnendu Chakrabarty
    A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10230-10237 [Conf]
  27. Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel
    An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:382-386 [Conf]
  28. Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty
    EBIST: A Novel Test Generator with Built-In Fault Detection Capability. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10224-10229 [Conf]
  29. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Rapid Generation of Thermal-Safe Test Schedules. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:840-845 [Conf]
  30. Anuja Sehgal, Krishnendu Chakrabarty
    Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:422-427 [Conf]
  31. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:285-290 [Conf]
  32. Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
    Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:50-55 [Conf]
  33. Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula
    Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1196-1201 [Conf]
  34. Fei Su, William L. Hwang, Krishnendu Chakrabarty
    Droplet routing in the synthesis of digital microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:323-328 [Conf]
  35. Mohammad H. Tehranipour, Mehrdad Nourani, Krishnendu Chakrabarty
    Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1284-1289 [Conf]
  36. Zhanglei Wang, Krishnendu Chakrabarty, Michael Gössel
    Test set enrichment using a probabilistic fault model and the theory of output deviations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1270-1275 [Conf]
  37. Ying Zhang, Krishnendu Chakrabarty
    Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10918-10925 [Conf]
  38. Ying Zhang, Krishnendu Chakrabarty
    Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1170-1175 [Conf]
  39. Yi Zou, Krishnendu Chakrabarty
    Fault-Tolerant Self-organization in Sensor Networks. [Citation Graph (0, 0)][DBLP]
    DCOSS, 2005, pp:191-205 [Conf]
  40. Krishnendu Chakrabarty
    Design and Test of Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:17- [Conf]
  41. Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:544-551 [Conf]
  42. Krishnendu Chakrabarty
    Reconfiguration-Based Defect Tolerance for Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:- [Conf]
  43. Ying Zhang, Krishnendu Chakrabarty
    Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:320-327 [Conf]
  44. Krishnendu Chakrabarty, John P. Hayes
    Balance Testing of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:350-359 [Conf]
  45. Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud
    An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:105-110 [Conf]
  46. Vamsee K. Pamula, Krishnendu Chakrabarty
    Cooling of integrated circuits using droplet-based microfluidics. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:84-87 [Conf]
  47. Krishnendu Chakrabarty
    Test scheduling for core-based systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:391-394 [Conf]
  48. Krishnendu Chakrabarty, J. E. Chen
    A cocktail approach on random access scan toward low power and high efficiency test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:94-99 [Conf]
  49. Fei Su, Krishnendu Chakrabarty
    Architectural-level synthesis of digital microfluidics-based biochips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:223-228 [Conf]
  50. Anuja Sehgal, Krishnendu Chakrabarty
    Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:88-93 [Conf]
  51. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
    TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:95-99 [Conf]
  52. Vishnu Swaminathan, Krishnendu Chakrabarty
    Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:21-25 [Conf]
  53. Ying Zhang, Krishnendu Chakrabarty, Vishnu Swaminathan
    Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:209-214 [Conf]
  54. Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty
    On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:387-396 [Conf]
  55. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
    A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:137-142 [Conf]
  56. Yi Zou, Krishnendu Chakrabarty
    Sensor Deployment and Target Localization Based on Virtual Forces. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2003, pp:- [Conf]
  57. Chunsheng Liu, Krishnendu Chakrabarty
    Compact Dictionaries for Fault Diagnosis in BIST. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:105-110 [Conf]
  58. Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton
    Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:173-178 [Conf]
  59. Krishnendu Chakrabarty, John P. Hayes
    Efficient Test-Response Compression for Multiple-Output Cicuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:501-510 [Conf]
  60. Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray
    Test Width Compression for Built-In Self Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:328-337 [Conf]
  61. Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
    Optimal Space Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:834-843 [Conf]
  62. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Test wrapper and test access mechanism co-optimization for system-on-chip. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1023-1032 [Conf]
  63. Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1159-1168 [Conf]
  64. Lei Li, Krishnendu Chakrabarty
    Deterministic BIST Based on a Reconfigurable Interconnection Network. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:460-469 [Conf]
  65. Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty
    A Set of Benchmarks fo Modular Testing of SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:519-528 [Conf]
  66. Fei Su, Krishnendu Chakrabarty
    Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:883-892 [Conf]
  67. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1203-1212 [Conf]
  68. Fei Su, Sule Ozev, Krishnendu Chakrabarty
    Testing of Droplet-Based Microelectrofluidic Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1192-1200 [Conf]
  69. Krishnendu Chakrabarty, S. Sitharama Iyengar, Hairong Qi, Eungchun Cho
    Coding Theory Framework for Target Location in Distributed Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ITCC, 2001, pp:130-0 [Conf]
  70. Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara
    Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  71. Yi Zou, Krishnendu Chakrabarty
    Energy-Aware Target Localization in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    PerCom, 2003, pp:60-0 [Conf]
  72. Vishnu Swaminathan, Charles B. Schweizer, Krishnendu Chakrabarty, Amil A. Patel
    Experiences in Implementing an Energy-Driven Task Scheduler in RT-Linux. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2002, pp:229-238 [Conf]
  73. Krishnendu Chakrabarty
    Design, Testing, and Applications of Digital Microfluidics-Based Biochips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:221-226 [Conf]
  74. Krishnendu Chakrabarty, Andrew Exnicios, Rajatish Mukherjee
    Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:431-0 [Conf]
  75. Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan
    Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:53-58 [Conf]
  76. Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama Mohan
    An ECO Technique for Removing Crosstalk Violations in Clock Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:283-288 [Conf]
  77. Tao Xu, Krishnendu Chakrabarty, Fei Su
    Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:647-652 [Conf]
  78. Sudarshan Bahukudumbi, Krishnendu Chakrabarty
    Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:459-464 [Conf]
  79. Anshuman Chandra, Krishnendu Chakrabarty
    Test Data Compression for System-on-a-Chip Using Golomb Codes. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:113-120 [Conf]
  80. Anshuman Chandra, Krishnendu Chakrabarty
    Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:42-47 [Conf]
  81. Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina
    How Effective are Compression Codes for Reducing Test Data Volume? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:91-96 [Conf]
  82. Lei Li, Krishnendu Chakrabarty
    Test Data Compression Using Dictionaries with Fixed-Length Indices. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:219-224 [Conf]
  83. Krishnendu Chakrabarty
    Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:127-136 [Conf]
  84. Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
    Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:22-27 [Conf]
  85. Fei Su, Krishnendu Chakrabarty
    Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:321-326 [Conf]
  86. Vikram Iyengar, Krishnendu Chakrabarty
    Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:368-374 [Conf]
  87. Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar
    Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:299-312 [Conf]
  88. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:253-258 [Conf]
  89. Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
    Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:418-423 [Conf]
  90. A. Morozov, Michael Gössel, Krishnendu Chakrabarty, Bhargab B. Bhattacharya
    Design of Parameterizable Error-Propagating Space Compactors for Response Observation. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:48-53 [Conf]
  91. Markus Seuring, Krishnendu Chakrabarty
    Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:213-220 [Conf]
  92. Yi Zou, Krishnendu Chakrabarty
    Target localization based on energy considerations in distributed sensor networks. [Citation Graph (0, 0)][DBLP]
    Ad Hoc Networks, 2003, v:1, n:2-3, pp:261-272 [Journal]
  93. Krishnendu Chakrabarty, Erik Jan Marinissen
    How Useful are the ITC 02 SoC Test Benchmarks? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:120- [Journal]
  94. Anshuman Chandra, Krishnendu Chakrabarty
    Test Resource Partitioning for SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:80-91 [Journal]
  95. Vikram Iyengar, Krishnendu Chakrabarty
    An Efficient Finite-State Machine Implementation of Huffman Decoders. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1997, v:64, n:6, pp:271-275 [Journal]
  96. Mark G. Karpovsky, Krishnendu Chakrabarty, Lev B. Levitin, Dimiter R. Avresky
    On the Covering of Vertices for Fault Diagnosis in Hypercubes. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1999, v:69, n:2, pp:99-103 [Journal]
  97. Krishnendu Chakrabarty, Jun Zeng
    Design automation for microfluidics-based biochips. [Citation Graph (0, 0)][DBLP]
    JETC, 2005, v:1, n:3, pp:186-223 [Journal]
  98. Fei Su, Krishnendu Chakrabarty
    Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:2, pp:104-128 [Journal]
  99. Yi Zou, Krishnendu Chakrabarty
    Uncertainty-aware and coverage-oriented deployment for sensor networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2004, v:64, n:7, pp:788-798 [Journal]
  100. Krishnendu Chakrabarty, S. Sitharama Iyengar, Hairong Qi, Eungchun Cho
    Grid Coverage for Surveillance and Target Location in Distributed Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:12, pp:1448-1453 [Journal]
  101. Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
    Optimal Zero-Aliasing Space Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1171-1187 [Journal]
  102. Anshuman Chandra, Krishnendu Chakrabarty
    Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:1076-1088 [Journal]
  103. Vikram Iyengar, Krishnendu Chakrabarty
    Test Bus Sizing for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:5, pp:449-459 [Journal]
  104. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:12, pp:1619-1632 [Journal]
  105. Chunsheng Liu, Krishnendu Chakrabarty
    Compact Dictionaries for Fault Diagnosis in Scan-BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:775-780 [Journal]
  106. Harshavardhan Sabbineni, Krishnendu Chakrabarty
    Location-Aided Flooding: An Energy-Efficient Data Dissemination Protocol for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:1, pp:36-46 [Journal]
  107. Anuja Sehgal, Krishnendu Chakrabarty
    Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:1, pp:120-133 [Journal]
  108. Yi Zou, Krishnendu Chakrabarty
    A Distributed Coverage- and Connectivity-Centric Technique for Selecting Active Nodes in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:8, pp:978-991 [Journal]
  109. Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty
    Synthesis of single-output space compactors for scan-based sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1171-1179 [Journal]
  110. Krishnendu Chakrabarty
    Test scheduling for core-based systems using mixed-integer linearprogramming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1163-1174 [Journal]
  111. Krishnendu Chakrabarty
    Zero-aliasing space compaction using linear compactors with bounded overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:452-457 [Journal]
  112. Krishnendu Chakrabarty, John P. Hayes
    Test response compaction using multiplexed parity trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1399-1408 [Journal]
  113. Krishnendu Chakrabarty, John P. Hayes
    On the quality of accumulator-based compaction of test responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:916-922 [Journal]
  114. Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski
    Test planning for modular testing of hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:435-448 [Journal]
  115. Krishnendu Chakrabarty, Brian T. Murray
    Design of built-in test generator circuits using width compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1044-1051 [Journal]
  116. Anshuman Chandra, Krishnendu Chakrabarty
    System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:355-368 [Journal]
  117. Anshuman Chandra, Krishnendu Chakrabarty
    Low-power scan testing and test data compression forsystem-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:597-604 [Journal]
  118. Anshuman Chandra, Krishnendu Chakrabarty
    Test data compression and decompression based on internal scanchains and Golomb coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:715-722 [Journal]
  119. Anshuman Chandra, Krishnendu Chakrabarty
    A unified approach to reduce SOC test data volume, scan power and testing time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:352-363 [Journal]
  120. Jie Ding, Krishnendu Chakrabarty, Richard B. Fair
    Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1463-1468 [Journal]
  121. Vikram Iyengar, Krishnendu Chakrabarty
    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1088-1094 [Journal]
  122. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient test access mechanism optimization for system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:635-643 [Journal]
  123. Lei Li, Krishnendu Chakrabarty
    Test set embedding for deterministic BIST using a reconfigurable interconnection network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1289-1305 [Journal]
  124. Chunsheng Liu, Krishnendu Chakrabarty
    Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:593-604 [Journal]
  125. Chunsheng Liu, Krishnendu Chakrabarty
    Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1447-1459 [Journal]
  126. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2502-2512 [Journal]
  127. Fei Su, Krishnendu Chakrabarty, Richard B. Fair
    Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:2, pp:211-223 [Journal]
  128. Vishnu Swaminathan, Krishnendu Chakrabarty
    Energy-conscious, deterministic I/O device scheduling in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:847-858 [Journal]
  129. Vishnu Swaminathan, Krishnendu Chakrabarty
    Network flow techniques for dynamic voltage scaling in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1385-1398 [Journal]
  130. Ying Zhang, Krishnendu Chakrabarty
    A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:111-125 [Journal]
  131. Tianhao Zhang, Krishnendu Chakrabarty, Richard B. Fair
    Design of reconfigurable composite microsystems based on hardware/software codesign principles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:987-995 [Journal]
  132. Tianhao Zhang, Krishnendu Chakrabarty, Richard B. Fair
    Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:843-858 [Journal]
  133. Vishnu Swaminathan, Krishnendu Chakrabarty
    Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:141-167 [Journal]
  134. Ying Zhang, Krishnendu Chakrabarty
    Dynamic adaptation for fault tolerance and power management in embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:336-360 [Journal]
  135. Yi Zou, Krishnendu Chakrabarty
    Sensor deployment and target localization in distributed sensor networks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:61-91 [Journal]
  136. Mark G. Karpovsky, Krishnendu Chakrabarty, Lev B. Levitin
    On a New Class of Codes for Identifying Vertices in Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Theory, 1998, v:44, n:2, pp:599-611 [Journal]
  137. Qishi Wu, Nageswara S. V. Rao, Jacob Barhen, S. Sitharama Iyengar, Vijay K. Vaishnavi, Hairong Qi, Krishnendu Chakrabarty
    On Computing Mobile Agent Routes for Data Fusion in Distributed Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Knowl. Data Eng., 2004, v:16, n:6, pp:740-753 [Journal]
  138. Fei Su, Krishnendu Chakrabarty
    Module placement for fault-tolerant microfluidics-based biochips. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:682-710 [Journal]
  139. Krishnendu Chakrabarty
    Optimal test access architectures for system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:1, pp:26-49 [Journal]
  140. Lei Li, Krishnendu Chakrabarty, Nur A. Touba
    Test data compression using dictionaries with selective entries and fixed-length indices. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:470-490 [Journal]
  141. Fei Su, Sule Ozev, Krishnendu Chakrabarty
    Concurrent testing of digital microfluidics-based biochips. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:442-464 [Journal]
  142. Hairong Qi, S. Sitharama Iyengar, Krishnendu Chakrabarty
    Multiresolution data integration using mobile agents in distributed sensor networks. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part C, 2001, v:31, n:3, pp:383-391 [Journal]
  143. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
    Test infrastructure design for mixed-signal SOCs with wrapped analog cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:292-304 [Journal]
  144. Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
    SOC test planning using virtual test access architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1263-1276 [Journal]
  145. Chunsheng Liu, Krishnendu Chakrabarty
    Design and analysis of compact dictionaries for diagnosis in scan-BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:979-984 [Journal]
  146. Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty
    Nine-coded compression technique for testing embedded cores in SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:719-731 [Journal]
  147. Tao Xu, Krishnendu Chakrabarty
    Integrated Droplet Routing in the Synthesis of Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:948-953 [Conf]
  148. Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
    SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:676-681 [Conf]
  149. Tao Xu, Krishnendu Chakrabarty
    A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:552-557 [Conf]
  150. Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang
    SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:201-206 [Conf]
  151. Tao Xu, Krishnendu Chakrabarty
    Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:63-68 [Conf]
  152. Zhanglei Wang, Krishnendu Chakrabarty, Michael Bienek
    A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:125-130 [Conf]
  153. Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula
    Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  154. Fei Su, Krishnendu Chakrabarty
    Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  155. Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
    Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  156. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Rapid Generation of Thermal-Safe Test Schedules [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  157. Yi Zou, Krishnendu Chakrabarty
    Distributed Mobility Management for Target Tracking in Mobile Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2007, v:6, n:8, pp:872-887 [Journal]
  158. Lei Li, Zhanglei Wang, Krishnendu Chakrabarty
    Scan-BIST based on cluster analysis and the encoding of repeating sequences. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]
  159. Sudarshan Bahukudumbi, Krishnendu Chakrabarty
    Wafer-Level Modular Testing of Core-Based SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1144-1154 [Journal]
  160. Krishnendu Chakrabarty, John P. Hayes
    Cumulative balance testing of logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:72-83 [Journal]
  161. Krishnendu Chakrabarty, John P. Hayes
    Zero-aliasing space compaction of test responses using multiple parity signatures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:309-313 [Journal]
  162. Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
    Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:633-636 [Journal]
  163. Fei Su, Sule Ozev, Krishnendu Chakrabarty
    Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:199-210 [Journal]
  164. Zhanglei Wang, Krishnendu Chakrabarty
    Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:145-161 [Journal]
  165. Fei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty
    Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:219-233 [Journal]

  166. Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. [Citation Graph (, )][DBLP]


  167. AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. [Citation Graph (, )][DBLP]


  168. Compact Test Generation for Small-Delay Defects Using Testable-Path Information. [Citation Graph (, )][DBLP]


  169. Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. [Citation Graph (, )][DBLP]


  170. Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips. [Citation Graph (, )][DBLP]


  171. Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips. [Citation Graph (, )][DBLP]


  172. Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. [Citation Graph (, )][DBLP]


  173. Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. [Citation Graph (, )][DBLP]


  174. Cross-contamination avoidance for droplet routing in digital microfluidic biochips. [Citation Graph (, )][DBLP]


  175. Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects. [Citation Graph (, )][DBLP]


  176. Generation of compact test sets with high defect coverage. [Citation Graph (, )][DBLP]


  177. Defect aware X-filling for low-power scan testing. [Citation Graph (, )][DBLP]


  178. High-quality pattern selection for screening small-delay defects considering process variations and crosstalk. [Citation Graph (, )][DBLP]


  179. Soft error-aware design optimization of low power and time-constrained embedded systems. [Citation Graph (, )][DBLP]


  180. Dual-threshold pass-transistor logic design. [Citation Graph (, )][DBLP]


  181. Design and optimization of a digital microfluidic biochip for protein crystallization. [Citation Graph (, )][DBLP]


  182. Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. [Citation Graph (, )][DBLP]


  183. Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD. [Citation Graph (, )][DBLP]


  184. Test-access mechanism optimization for core-based three-dimensional SOCs. [Citation Graph (, )][DBLP]


  185. On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors. [Citation Graph (, )][DBLP]


  186. Automated design of digital microfluidic lab-on-chip under pin-count constraints. [Citation Graph (, )][DBLP]


  187. Privacy-Preserving Detection of Sybil Attacks in Vehicular Ad Hoc Networks. [Citation Graph (, )][DBLP]


  188. Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips. [Citation Graph (, )][DBLP]


  189. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore. [Citation Graph (, )][DBLP]


  190. Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. [Citation Graph (, )][DBLP]


  191. Test-Pattern Grading and Pattern Selection for Small-Delay Defects. [Citation Graph (, )][DBLP]


  192. Test-architecture optimization for TSV-based 3D stacked ICs. [Citation Graph (, )][DBLP]


  193. Diverse Routing: Exploiting Social Behavior for Routing in Delay-Tolerant Networks. [Citation Graph (, )][DBLP]


  194. Digital Microfluidic Logic Gates. [Citation Graph (, )][DBLP]


  195. Guest Editors' Introduction: Biochips and Integrated Biosensor Platforms. [Citation Graph (, )][DBLP]


  196. A Digital-Microfluidic Approach to Chip Cooling. [Citation Graph (, )][DBLP]


  197. Test Challenges for 3D Integrated Circuits. [Citation Graph (, )][DBLP]


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