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## Search the dblp DataBase
Atsushi Takahashi:
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## Publications of Author- Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani
**Air-Pressure-Model-Based Fast Algorithms for General Floorplan.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 1998, pp:563-570 [Conf] - Bakhtiar Affendi Rosdi, Atsushi Takahashi
**Low area pipelined circuits by multi-clock cycle paths and clock scheduling.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:260-265 [Conf] - Yoichi Tomioka, Atsushi Takahashi
**Monotonic parallel and orthogonal routing for single-layer ball grid array packages.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:642-647 [Conf] - Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
**Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 1999, pp:125-0 [Conf] - Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
**Optimal integer delay budgeting on directed acyclic graphs.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:920-925 [Conf] - Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
**Clustering based fast clock scheduling for light clock-tree.**[Citation Graph (0, 0)][DBLP] DATE, 2001, pp:240-245 [Conf] - Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
**Incremental Timing Budget Management in Programmable Systems.**[Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:240-246 [Conf] - Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
**A fast clock scheduling for peak power reduction in LSI.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:582-587 [Conf] - Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani
**Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:260-265 [Conf] - Yusuke Maeda, Atsushi Takahashi, Takayuki Hara, Tamio Arai
**Human-Robot Cooperation with Mechanical Interaction Based on Rhythm Entrainment -Realization of Cooperative Rope Turning.**[Citation Graph (0, 0)][DBLP] ICRA, 2001, pp:3477-3482 [Conf] - Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
**Mixed-Searching and Proper-Path-Width.**[Citation Graph (0, 0)][DBLP] ISA, 1991, pp:61-71 [Conf] - Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan
**Enumerating the min-cuts for applications to graph extraction under size constraints.**[Citation Graph (0, 0)][DBLP] ISCAS (6), 1999, pp:174-177 [Conf] - Yukiko Kubo, Atsushi Takahashi
**A global routing method for 2-layer ball grid array packages.**[Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:36-43 [Conf] - Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi
**A practical clock tree synthesis for semi-synchronous circuits.**[Citation Graph (0, 0)][DBLP] ISPD, 2000, pp:159-164 [Conf] - Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake
**Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:11- [Conf] - Yusuke Maeda, Atsushi Takahashi, Takayuki Hara, Tamio Arai
**Human-robot cooperative rope turning--an example of mechanical coordination through rhythm entrainment.**[Citation Graph (0, 0)][DBLP] Advanced Robotics, 2003, v:17, n:1, pp:67-78 [Journal] - Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
**Optimal integer delay-budget assignment on directed acyclic graphs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1184-1199 [Journal] - Yukiko Kubo, Atsushi Takahashi
**Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:725-733 [Journal] - Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
**Mixed Searching and Proper-Path-Width.**[Citation Graph (0, 0)][DBLP] Theor. Comput. Sci., 1995, v:137, n:2, pp:253-268 [Journal] - Yukihide Kohira, Atsushi Takahashi
**A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1795-1798 [Conf] - Y. Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, A. Takahashi
**Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
**Minimal acyclic forbidden minors for the family of graphs with bounded path-width.**[Citation Graph (0, 0)][DBLP] Discrete Mathematics, 1994, v:127, n:1-3, pp:293-304 [Journal] **A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound.**[Citation Graph (, )][DBLP]**Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages.**[Citation Graph (, )][DBLP]**ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.**[Citation Graph (, )][DBLP]**Bayesian Network for Future Home Energy Consumption.**[Citation Graph (, )][DBLP]**Numerical Experimentation on Structure Simplification in Bayesian Network.**[Citation Graph (, )][DBLP]**Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits.**[Citation Graph (, )][DBLP]
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