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Yoji Kajitani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani
    Air-Pressure-Model-Based Fast Algorithms for General Floorplan. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:563-570 [Conf]
  2. Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
    Abstraction and optimization of consistent floorplanning with pillar block constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:19-24 [Conf]
  3. Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
    Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:467-472 [Conf]
  4. Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
    Self-reforming routing for stochastic search in VLSI interconnection layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:87-92 [Conf]
  5. Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani
    Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:571-576 [Conf]
  6. Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
    Multi-level placement with circuit schema based clustering in analog IC layouts. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:406-411 [Conf]
  7. Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
    Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:125-0 [Conf]
  8. Xuliang Zhang, Yoji Kajitani
    Space-planning: placement of modules with controlled empty area by single-sequence. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:25-30 [Conf]
  9. Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin
    An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:61-68 [Conf]
  10. Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
    The oct-touched tile: a new architecture for shape-based routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:126-129 [Conf]
  11. Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
    Equidistance routing in high-speed VLSI layout design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:220-223 [Conf]
  12. Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
    A device-level placement with multi-directional convex clustering. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:196-201 [Conf]
  13. Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani
    How does partitioning matter for 3D floorplanning? [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:73-78 [Conf]
  14. Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
    Rectangle-packing-based module placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:472-479 [Conf]
  15. Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
    Module placement on BSG-structure and IC layout applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:484-491 [Conf]
  16. Shigetoshi Nakatake, Yoji Kajitani
    Channel-driven global routing with consistent placement (extended abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:350-355 [Conf]
  17. Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita
    The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:418-425 [Conf]
  18. Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani
    The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:267-274 [Conf]
  19. Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani
    Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:260-265 [Conf]
  20. Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
    Mixed-Searching and Proper-Path-Width. [Citation Graph (0, 0)][DBLP]
    ISA, 1991, pp:61-71 [Conf]
  21. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
    The Totally-Perfect Bipartite Graph and Its Construction. [Citation Graph (0, 0)][DBLP]
    ISAAC, 1994, pp:541-549 [Conf]
  22. Wayne Wei-Ming Dai, Yoji Kajitani, Yorihiko Hirata
    Optimal single hop multiple bus networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2541-2544 [Conf]
  23. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
    Design of Optimum Totally Perfect Connection-Blocks of FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:221-224 [Conf]
  24. Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani
    Fixed-outline floorplanning with constraints through instance augmentation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1883-1886 [Conf]
  25. Xuliang Zhang, Yoji Kajitani
    Theory of T-junction floorplans in terms of single-sequence. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:341-344 [Conf]
  26. Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani
    A new approach based on LFF for optimization of dynamic hardware reconfigurations. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1210-1213 [Conf]
  27. Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
    Consistent floorplanning with super hierarchical constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:144-149 [Conf]
  28. Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani
    Adaptive Porting of Analog IPs with Reusable Conservative Properties. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:18-23 [Conf]
  29. Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake
    Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:11- [Conf]
  30. Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
    Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:467-472 [Conf]
  31. Yoji Kajitani, Jun Dong Cho, Majid Sarrafzadeh
    New Approximation Results on Graph Matching and related Problems. [Citation Graph (0, 0)][DBLP]
    WG, 1994, pp:343-358 [Conf]
  32. Tadashi Arai, Shuichi Ueno, Yoji Kajitani
    Generalization of aTheorem on the Parametric Maximum Flow Problem. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1993, v:41, n:1, pp:69-74 [Journal]
  33. Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
    Equidistance routing in high-speed VLSI layout design. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:439-449 [Journal]
  34. Magnús M. Halldórsson, Shuichi Ueno, Hiroshi Nakao, Yoji Kajitani
    Approximating Steiner trees in graphs with restricted weights. [Citation Graph (0, 0)][DBLP]
    Networks, 1998, v:31, n:4, pp:283-292 [Journal]
  35. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
    Design of minimum and uniform bipartites for optimum connection blocks of FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1377-1383 [Journal]
  36. Yoji Kajitani
    Order of Channels for Safe Routing and Optimal Compaction of Routing Area. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:4, pp:293-300 [Journal]
  37. Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
    Module packing based on the BSG-structure and IC layout applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:519-530 [Journal]
  38. Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
    Consistent floorplanning with hierarchical superconstraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:42-49 [Journal]
  39. Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
    VLSI module placement based on rectangle-packing by the sequence-pair. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1518-1524 [Journal]
  40. Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
    Mixed Searching and Proper-Path-Width. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1995, v:137, n:2, pp:253-268 [Journal]
  41. Yoji Kajitani
    Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  42. Yoji Kajitani, Shuichi Ueno, Hiroshi Miyano
    Ordering of the elements of a matroid such that its consecutive w elements are independent. [Citation Graph (0, 0)][DBLP]
    Discrete Mathematics, 1988, v:72, n:1-3, pp:187-194 [Journal]
  43. Shuichi Ueno, Yoji Kajitani, Shin'ya Gotoh
    On the nonseparating independent set problem and feedback set problem for graphs with no vertex degree exceeding three. [Citation Graph (0, 0)][DBLP]
    Discrete Mathematics, 1988, v:72, n:1-3, pp:355-360 [Journal]
  44. Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
    Minimal acyclic forbidden minors for the family of graphs with bounded path-width. [Citation Graph (0, 0)][DBLP]
    Discrete Mathematics, 1994, v:127, n:1-3, pp:293-304 [Journal]

  45. Chip size estimation based on wiring area. [Citation Graph (, )][DBLP]


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