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A. B. Bhattacharyya :
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A. B. Bhattacharyya , Shrutin Ulman PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2002, pp:207-212 [Conf ] A. Bandyopadhyay , P. R. Verma , A. B. Bhattacharyya , M. J. Zarabi LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:339-342 [Conf ] A. B. Bhattacharyya , R. S. Rana , S. K. Guha , Rajendar Bahl , R. Anand , M. J. Zarabi , P. A. Govindacharyulu , U. Gupta , V. Mohan , Jatin Roy , Amul Atri A micropower analog hearing aid on low voltage CMOS digital process. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1996, pp:85-89 [Conf ] A. B. Bhattacharyya Compact MOSFET Models for Low Power Analog CMOS Design. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2005, pp:15- [Conf ] A. B. Bhattacharyya , Saudas Dey Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and Filters. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:164-168 [Conf ] A. B. Bhattacharyya , Shrutin Ulman PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2002, pp:207-212 [Conf ] Navneet K. Jain , V. C. Prasad , A. B. Bhattacharyya Delay time sensitivity in nonlinear monotone RC trees. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:554-560 [Journal ] Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs