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Shekhar Borkar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shekhar Borkar
    Low power design challenges for the decade (invited talk). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:293-296 [Conf]
  2. Shekhar Borkar
    Electronics beyond nano-scale CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:807-808 [Conf]
  3. Shekhar Borkar, Tanay Karnik, Vivek De
    Design and reliability challenges in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:75- [Conf]
  4. Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De
    Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:338-342 [Conf]
  5. Andrew B. Kahng, Shekhar Borkar, John Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
    Nanometer design: place your bets. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:546-547 [Conf]
  6. Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
    Panel: Is Nanometer Design Under Control? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:591-592 [Conf]
  7. Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
    Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:486-491 [Conf]
  8. George Sery, Shekhar Borkar, Vivek De
    Life is CMOS: why chase the life after? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:78-83 [Conf]
  9. Vivek De, Shekhar Borkar
    Low power and high performance design challenges in future technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:1-6 [Conf]
  10. Ram Krishnamurthy, Mark Anders, K. Soumyanath, Shekhar Borkar
    Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:43-44 [Conf]
  11. Tanay Karnik, Shekhar Borkar, Vivek De
    Sub-90nm technologies: challenges and opportunities for CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:203-206 [Conf]
  12. Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
    Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:100-105 [Conf]
  13. Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica S. Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb
    Supporting Systolic and Memory Communciation in iWarp. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:70-81 [Conf]
  14. Vivek De, Shekhar Borkar
    Technology and design challenges for low power and high performance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:163-168 [Conf]
  15. Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar
    A low-leakage dynamic multi-ported register file in 0.13mm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:68-71 [Conf]
  16. Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
    Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:122-127 [Conf]
  17. Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De
    Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:207-212 [Conf]
  18. Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
    Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:252-254 [Conf]
  19. Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar
    Scaling of stack effect and its application for leakage reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:195-200 [Conf]
  20. Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan
    Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:19-23 [Conf]
  21. James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
    Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:147-152 [Conf]
  22. Shekhar Borkar, Robert Cohn, George W. Cox, Sha Gleason, Thomas R. Gross
    Warp: an integrated solution of high-speed parallel computing. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:330-339 [Conf]
  23. Shekhar Borkar
    Exponential Challenges, Exponential Rewards - The future of Moore's Law. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:2- [Conf]
  24. Shekhar Borkar
    Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law. [Citation Graph (0, 0)][DBLP]
    ACM Queue, 2003, v:1, n:7, pp:26-33 [Journal]
  25. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
    A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:646-649 [Journal]
  26. Shekhar Borkar
    Thousand Core ChipsA Technology Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:746-749 [Conf]
  27. Shekhar Borkar, Norman P. Jouppi, Per Stenström
    Microprocessors in the era of terascale integration. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:237-242 [Conf]
  28. Shekhar Borkar
    Introduction to panel discussion Probabilistic & statistical design - the wave of the future. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:- [Conf]
  29. Yatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar
    A 5-GHz Mesh Interconnect for a Teraflops Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:51-61 [Journal]
  30. Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, M. Stan, Vivek De
    Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:91-95 [Journal]

  31. Custom is from Venus and synthesis from Mars. [Citation Graph (, )][DBLP]

  32. Design perspectives on 22nm CMOS and beyond. [Citation Graph (, )][DBLP]

  33. Future of on-chip interconnection architectures. [Citation Graph (, )][DBLP]

  34. Tackling variability and reliability challenges. [Citation Graph (, )][DBLP]

  35. Thousand-Core Chips [Roundtable]. [Citation Graph (, )][DBLP]

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