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Yuchun Ma: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    A buffer planning algorithm with congestion optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:615-620 [Conf]
  2. Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
    An automated design flow for 3D microarchitecture evaluation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:384-389 [Conf]
  3. Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    VLSI floorplanning with boundary constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:509-514 [Conf]
  4. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Buffer allocation algorithm with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:621-623 [Conf]
  5. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:387-392 [Conf]
  6. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Dynamic global buffer planning optimization based on detail block locating and congestion analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:806-811 [Conf]
  7. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:770-775 [Conf]
  8. Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
    An effective buffer planning algorithm for IP based fixed-outline SOC placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:564-569 [Conf]
  9. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
    VLSI block placement with alignment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6222-6225 [Conf]
  10. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Evaluating a bounded slice-line grid assignment in O(nlogn) time. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:708-711 [Conf]
  11. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
    Performance constrained floorplanning based on partial clustering [IC layout]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1863-1866 [Conf]
  12. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
    Arbitrary convex and concave rectilinear block packing based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:493-496 [Conf]
  13. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    An integrated floorplanning with an efficient buffer planning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:136-142 [Conf]
  14. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
    Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:628-633 [Conf]
  15. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
    Buffer Planning Algorithm Based on Partial Clustered Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:213-219 [Conf]
  16. Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
    Interconnect Power Optimization Based on Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:119-124 [Conf]
  17. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:387-392 [Conf]
  18. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with abutment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:65-77 [Journal]
  19. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
    Fast Evaluation of Bounded Slice-Line Grid. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:6, pp:973-980 [Journal]
  20. Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    General Floorplans with L/T-Shaped Blocks Using Corner Block List. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:922-926 [Journal]
  21. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
    Buffer planning as an Integral part of floorplanning with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:609-621 [Journal]
  22. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway compaction using corner block list and its applications with rectilinear blocks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:199-211 [Journal]
  23. Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
    A Fast 3D-BSG Algorithm for 3D Packing Problem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2044-2047 [Conf]
  24. Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
    An accurate and efficient probabilistic congestion estimation model in x architecture. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:25-32 [Conf]

  25. A novel thermal optimization flow using incremental floorplanning for 3D ICs. [Citation Graph (, )][DBLP]


  26. Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. [Citation Graph (, )][DBLP]


  27. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. [Citation Graph (, )][DBLP]


  28. LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. [Citation Graph (, )][DBLP]


  29. MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer. [Citation Graph (, )][DBLP]


  30. Multi-objective Floorplanning Based on Fuzzy Logic. [Citation Graph (, )][DBLP]


  31. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. [Citation Graph (, )][DBLP]


  32. Fine grain 3D integration for microarchitecture design through cube packing exploration. [Citation Graph (, )][DBLP]


  33. Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. [Citation Graph (, )][DBLP]


  34. IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. [Citation Graph (, )][DBLP]


  35. Simultaneous buffer and interlayer via planning for 3D floorplanning. [Citation Graph (, )][DBLP]


  36. Incremental power optimization for multiple supply voltage design. [Citation Graph (, )][DBLP]


  37. A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. [Citation Graph (, )][DBLP]


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