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Masaharu Imai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi
    A hardware/software codesign method for pipelined instruction set processor using adaptive database. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi
    A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:367-372 [Conf]
  3. M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Enabling RTOS simulation modeling in a system level design language. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:936-939 [Conf]
  4. Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
    One language or more?: how can we design an SoC at a system level? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:653-654 [Conf]
  5. Masaharu Imai, Eugenio Villar
    Future direction of synthesizability and interoperability of HDL's: part 1. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  6. Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai
    Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:649-654 [Conf]
  7. Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Synthesizable HDL generation method for configurable VLIW processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:842-845 [Conf]
  8. Eugenio Villar, Masaharu Imai
    Future direction of synthesizabilty and interoperability of HDL's: part 2. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  9. Masaharu Imai, Akira Kitajima
    Verification Challenges in Configurable Processor Design with ASIP Meister. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:2- [Conf]
  10. Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa
    Pack instruction generation for media pUsing multi-valued decision diagram. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:154-159 [Conf]
  11. Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi
    A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:527-532 [Conf]
  12. M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:554-559 [Conf]
  13. Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Architecture-Level Performance Estimation for IP-Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1002-1007 [Conf]
  14. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
    Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:81-86 [Conf]
  15. Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura
    Application of FHM-Based Design Method to Scalable 2-D DCT Processor. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1406-1409 [Conf]
  16. Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai
    VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2001, pp:400-409 [Conf]
  17. Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki
    Implementation of Parallel Prolog on Tree Machines. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:287-296 [Conf]
  18. Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi
    An ASIP instruction set optimization algorithm with functional module sharing constraint. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:526-532 [Conf]
  19. Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi
    PEAS-III: An ASIP Design Environment. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:430-436 [Conf]
  20. Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi
    An Integrated Design Environment for Application Specific Integrated Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:414-417 [Conf]
  21. Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura
    The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1984, pp:174-182 [Conf]
  22. H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2004, pp:824-830 [Conf]
  23. Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai
    S-sequence: a new floorplan representation method preserving room abutment relationships. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:505-508 [Conf]
  24. Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai
    Design of Application Specific CISC Using PEAS-III. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:12-17 [Conf]
  25. Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai
    A Code Selection Method for SIMD Processors with PACK Instructions. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:66-80 [Conf]
  26. Masaharu Imai, Eugenio Villar
    ASPDAC 1995: HDL synthesizability and interoperability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:1, pp:3-4 [Journal]
  27. Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:290-295 [Conf]
  28. M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  29. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
    Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  30. Operation shuffling over cycle boundaries for low energy L0 clustering. [Citation Graph (, )][DBLP]


  31. A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. [Citation Graph (, )][DBLP]


  32. Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. [Citation Graph (, )][DBLP]


  33. A low power VLIW processor generation method by means of extracting non-redundant activation conditions. [Citation Graph (, )][DBLP]


  34. A hardware/software partitioning algorithm for pipelined instruction set processor. [Citation Graph (, )][DBLP]


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