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Jer-Min Jou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
    Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:185-188 [Conf]
  2. Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang
    A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:205-208 [Conf]
  3. Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau
    A New Pipelined Architecture for Fuzzy Color Correction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:209-0 [Conf]
  4. Jer-Min Jou, Shung-Chih Chen
    A fast and memory-efficient diagnostic fault simulation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:723-726 [Conf]
  5. Jer-Min Jou, Shiann-Rong Kuang
    Library-Adaptively Integrated Data Path Synthesis for DSP Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:379-382 [Conf]
  6. Jer-Min Jou, Shung-Chih Chen
    Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2004-2007 [Conf]
  7. Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen
    A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:85-88 [Conf]
  8. Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang
    Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:45-48 [Conf]
  9. Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu
    Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:529-532 [Conf]
  10. Jer Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun
    A Novel Reconfigurable Computation Unit for DSP Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:439-444 [Conf]
  11. Shung-Chih Chen, Jer-Min Jou
    Serial diagnostic fault simulation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:23, n:2, pp:157-170 [Journal]
  12. Shung-Chih Chen, Jer-Min Jou
    Diagnostic fault simulation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:299-308 [Journal]
  13. Pei-Yin Chen, Jer-Min Jou
    An efficient blocking-matching algorithm based on fuzzy reasoning. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part B, 2001, v:31, n:2, pp:253-259 [Journal]
  14. Jer-Min Jou, Pei-Yin Chen, Sheng-Fu Yang
    An adaptive fuzzy logic controller: its VLSI architecture and applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:52-60 [Journal]
  15. Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen
    Design of a dynamic pipelined architecture for fuzzy color correction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:924-929 [Journal]

  16. New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. [Citation Graph (, )][DBLP]

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