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Malgorzata Chrzanowska-Jeske: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang
    Substrate noise modeling in early floorplanning of MS-SOCs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:819-823 [Conf]
  2. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
    Detecting support-reducing bound sets using two-cofactor symmetries. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:266-271 [Conf]
  3. Andisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski
    A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:321-326 [Conf]
  4. Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:510-515 [Conf]
  5. Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
    Regular Realization of Symmetric Functions Using Reversible Logic. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:245-253 [Conf]
  6. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings
    Board-level multiterminal net assignment. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:130-135 [Conf]
  7. Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske
    Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:100-106 [Conf]
  8. Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
    Modeling of substrate noise block properties for early prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:3015-3018 [Conf]
  9. Malgorzata Chrzanowska-Jeske, S. Goller, I. Schafer
    An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1782-1785 [Conf]
  10. Malgorzata Chrzanowska-Jeske, Alan Mishchenko
    Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4721-4724 [Conf]
  11. Malgorzata Chrzanowska-Jeske, Benyi Wang, G. Greenwood
    Floorplanning with performance-based clustering. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:724-727 [Conf]
  12. Ning Song, Malgorzata Chrzanowska-Jeske
    Output Column Folding for Cellular-Architecture FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:237-240 [Conf]
  13. Tao Wan, Malgorzata Chrzanowska-Jeske
    Generating random benchmark circuits for floorplanning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:345-348 [Conf]
  14. Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske
    Graph-based approach to evaluate net routability of a floorplan. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:465-468 [Conf]
  15. Wei Wang, Malgorzata Chrzanowska-Jeske
    A global approach to the variable ordering problem in PSBDDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:117-120 [Conf]
  16. Malgorzata Chrzanowska-Jeske
    Regular symmetric arrays for non-symmetric functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:391-394 [Conf]
  17. Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang
    Substrate noise-aware floorplanning for mixed-signal SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:445-448 [Conf]
  18. Marek A. Perkowski, Malgorzata Chrzanowska-Jeske
    Multiple-Valued-Input TANT Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:334-341 [Conf]
  19. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani
    Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:56-61 [Conf]
  20. Tao Wan, Malgorzata Chrzanowska-Jeske
    Prediction of interconnect net-degree distribution based on Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:107-114 [Conf]
  21. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Using simulation and satisfiability to compute flexibilities in Boolean networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:743-755 [Journal]
  22. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
    Integrated floorplanning with buffer/channel insertion for bus-based designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:730-741 [Journal]
  23. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
    Linear cofactor relationships in Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1011-1023 [Journal]
  24. Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
    Estimation of supply current spectrum for early noise evaluation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  25. Tao Wan, Malgorzata Chrzanowska-Jeske
    A novel net-degree distribution model and its application to floorplanning benchmark generation. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:420-433 [Journal]
  26. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola
    Board-level multiterminal net assignment for the partial cross-bar architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:511-514 [Journal]

  27. Layout synthesis for datapath designs. [Citation Graph (, )][DBLP]


  28. Tree restructuring approach to mapping problem in cellular-architecture FPGAs. [Citation Graph (, )][DBLP]


  29. Carbon nanotube circuit design choices in the presence of metallic tubes. [Citation Graph (, )][DBLP]


  30. Optimization of active circuits for substrate noise suppression. [Citation Graph (, )][DBLP]


  31. Yield improvement of 3D ICs in the presence of defects in through signal vias. [Citation Graph (, )][DBLP]


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