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Juinn-Dar Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
    A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:600-605 [Conf]
  2. Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
    FSM-based transaction-level functional coverage for interface compliance verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:448-453 [Conf]
  3. Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
    Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:712-717 [Conf]
  4. Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao
    Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:65-69 [Conf]
  5. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
    Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:359-363 [Conf]
  6. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
    An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:13-17 [Conf]
  7. Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
    Verification on Port Connections. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:830-836 [Conf]
  8. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
    On circuit clustering for area/delay tradeoff under capacity and pin constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:634-642 [Journal]
  9. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
    ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:392-400 [Journal]
  10. Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
    Unified functional decomposition via encoding for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:251-260 [Journal]

  11. CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. [Citation Graph (, )][DBLP]


  12. Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. [Citation Graph (, )][DBLP]


  13. A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. [Citation Graph (, )][DBLP]


  14. Fault Dictionary Size Reduction for Million-Gate Large Circuits. [Citation Graph (, )][DBLP]


  15. A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. [Citation Graph (, )][DBLP]


  16. Verification of Pin-Accurate Port Connections. [Citation Graph (, )][DBLP]


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