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Jing-Yang Jou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
    A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:600-605 [Conf]
  2. Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A new method for constructing IP level power model based on power sensitivity. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:135-140 [Conf]
  3. Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
    Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:280-283 [Conf]
  4. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
    An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:323-326 [Conf]
  5. Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang
    Hierarchical Floorplan Design on the Internet. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:189-192 [Conf]
  6. Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou
    Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:39-44 [Conf]
  7. Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou
    On compliance test of on-chip bus for SOC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:328-333 [Conf]
  8. Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
    An efficient design-for-verification technique for HDLs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:103-108 [Conf]
  9. Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
    FSM-based transaction-level functional coverage for interface compliance verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:448-453 [Conf]
  10. Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
    Layout techniques for on-chip interconnect inductance reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:269-273 [Conf]
  11. Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
    Collaboration between Industry and Academia in Test Research. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:17-0 [Conf]
  12. Jing-Yang Jou
    An effective BIST design for PLA. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:286-292 [Conf]
  13. Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo
    An Efficient PRPG Strategy By Utilizing Essential Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:199-204 [Conf]
  14. Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao
    Easily Testable Data Path Allocation Using Input/Output Registers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:142-0 [Conf]
  15. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
    Effective Error Diagnosis for RTL Designs in HDLs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:362-367 [Conf]
  16. Shing-Wu Tung, Jing-Yang Jou
    Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:402-407 [Conf]
  17. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:431-436 [Conf]
  18. Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
    Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:90-95 [Conf]
  19. Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
    Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:712-717 [Conf]
  20. Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou
    BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:409-414 [Conf]
  21. Kwang-Ting Cheng, Jing-Yang Jou
    A Single-State-Transition Fault Model for Sequential Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:226-229 [Conf]
  22. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
    Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:359-363 [Conf]
  23. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
    An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:13-17 [Conf]
  24. Jing-Yang Jou, Kwang-Ting Cheng
    Timing-Driven Partial Scan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:404-407 [Conf]
  25. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A power modeling and characterization method for the CMOS standard cell library. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:400-404 [Conf]
  26. Jing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A power modeling and characterization method for macrocells using structure information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:502-506 [Conf]
  27. Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou
    Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:417-419 [Conf]
  28. Jing-Yang Jou, Ming-Chang Nien
    Power Driven Partial Scan. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:642-647 [Conf]
  29. Chien-Nan Jimmy Liu, Jing-Yang Jou
    An Efficient Functional Coverage Test for HDL Descriptions at RTL. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:325-327 [Conf]
  30. Hen-Ming Lin, Jing-Yang Jou
    Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:364-0 [Conf]
  31. Jing-Yang Jou, Jacob A. Abraham
    Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:359-362 [Conf]
  32. Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang
    An efficient logic extraction algorithm using partitioning and circuit encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:249-252 [Conf]
  33. Yi-Wei Lin, Jing-Yang Jou
    An efficient approach for hierarchical submodule extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:237-240 [Conf]
  34. Che-Hua Shih, Jing-Yang Jou
    An efficient approach for error diagnosis in HDL design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:732-735 [Conf]
  35. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    SoC design integration by using automatic interconnection rectification. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:744-747 [Conf]
  36. Hen-Ming Lin, Jing-Yang Jou
    On tri-state buffer inference in HDL synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:45-48 [Conf]
  37. Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen
    Grouped input power sensitive transition an input sequence compaction technique for power estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:471-474 [Conf]
  38. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    An AVPG for SOC design verification with port order fault model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:259-262 [Conf]
  39. Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
    RLC effects on worst-case switching pattern for on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:945-948 [Conf]
  40. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
    Optimal reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:128-133 [Conf]
  41. Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou
    Automatic Functional Vector Generation Using the Interacting FSM Model. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:372-377 [Conf]
  42. Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
    Verification on Port Connections. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:830-836 [Conf]
  43. Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
    A Practical Approach to Cycle Bound Estimation for Property Checking. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:149-154 [Conf]
  44. Jing-Yang Jou, Kwang-Ting (Tim) Cheng
    Timing-Driven Partial Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:4, pp:52-59 [Journal]
  45. Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
    A Design-for-Verification Technique for Functional Pattern Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:48-55 [Journal]
  46. Chien-Nan Jimmy Liu, Jing-Yang Jou
    An Automatic Controller Extractor for HDL Descriptions at the RTL. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:72-77 [Journal]
  47. Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
    A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:111-120 [Journal]
  48. Heng-Liang Huang, Jing-Yang Jou
    Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:4, pp:333-350 [Journal]
  49. Shing-Wu Tung, Jing-Yang Jou
    A Logical Fault Model for Library Coherence Checking. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:567-586 [Journal]
  50. Jing-Yang Jou, Jacob A. Abraham
    Fault-Tolerant FFT Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:5, pp:548-561 [Journal]
  51. Chia-Chih Yen, Jing-Yang Jou
    An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1356-1366 [Journal]
  52. Kwang-Ting Cheng, Jing-Yang Jou
    A functional fault model for sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1065-1073 [Journal]
  53. Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo
    Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1015-1024 [Journal]
  54. Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
    An efficient heterogeneous tree multiplexer synthesis technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1622-1629 [Journal]
  55. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
    Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:999-1010 [Journal]
  56. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
    Simultaneous floor plan and buffer-block optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:694-703 [Journal]
  57. Hen-Ming Lin, Jing-Yang Jou
    On computing the minimum feedback vertex set of a directed graph bycontraction operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:295-307 [Journal]
  58. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    On automatic-verification pattern generation for SoC withport-order fault model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:466-479 [Journal]
  59. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1225-1232 [Journal]
  60. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    Automatic interconnection rectification for SoC design verification based on the port order fault model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:104-114 [Journal]
  61. Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou
    Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:172-176 [Journal]
  62. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
    Reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:88-103 [Journal]
  63. Jyh-Mou Tseng, Jing-Yang Jou
    Two-level logic minimization for low power. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:1, pp:52-69 [Journal]
  64. Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou
    A Tableless Approach for High-Level Power Modeling Using Neural Networks. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2007, v:23, n:1, pp:71-90 [Journal]
  65. Cheng-Yeh Wang, Chih-Bin Kuo, Jing-Yang Jou
    Hybrid Wordlength Optimization Methods of Pipelined FFT Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:8, pp:1105-1118 [Journal]
  66. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
    On circuit clustering for area/delay tradeoff under capacity and pin constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:634-642 [Journal]
  67. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A structure-oriented power modeling technique for macrocells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:380-391 [Journal]
  68. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
    ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:392-400 [Journal]
  69. Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
    Unified functional decomposition via encoding for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:251-260 [Journal]

  70. A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. [Citation Graph (, )][DBLP]


  71. RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. [Citation Graph (, )][DBLP]


  72. Verification of Pin-Accurate Port Connections. [Citation Graph (, )][DBLP]


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