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Publications of Author

1. Richard G. Guy, John S. Heidemann, Wai-Kei Mak, Thomas W. Page Jr., Gerald J. Popek, Dieter Rothmeier
   Implementation of the Ficus Replicated File System. [Citation Graph (4, 0)][DBLP]
   USENIX Summer, 1990, pp:63-72 [Conf]
   
2. Chien-Chang Chen, Wai-Kei Mak
   A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:777-782 [Conf]
   
3. Wai-Kei Mak
   Modern FPGA constrained placement. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:779-784 [Conf]
   
4. Wai-Kei Mak, D. F. Wong
   On Optimal Board-Level Routing for FPGA-Based Logic Emulation. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:552-556 [Conf]
   
5. Wai-Kei Mak
   I/O placement for FPGAs with multiple I/O standards. [Citation Graph (0, 0)][DBLP]
   FPGA, 2003, pp:51-57 [Conf]
   
6. Wai-Kei Mak, D. F. Wong
   Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). [Citation Graph (0, 0)][DBLP]
   FPGA, 1998, pp:260- [Conf]
   
7. Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
   Faster and more accurate wiring evaluation in interconnect-centric floorplanning. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:62-67 [Conf]
   
8. Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak
   Clustering based acyclic multi-way partitioning. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2003, pp:203-206 [Conf]
   
9. Wai-Kei Mak, D. F. Wong
   Board-level multi-terminal net routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:339-344 [Conf]
   
10. Wai-Kei Mak, D. F. Wong
    Minimum replication min-cut partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:205-210 [Conf]
    
11. Wai-Kei Mak, D. F. Wong
    Channel Segmentation Design for Symmentrical FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:496-501 [Conf]
    
12. Wai-Kei Mak, D. F. Wong
    A fast hypergraph minimum cut algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:170-173 [Conf]
    
13. Wai-Kei Mak
    Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:100-105 [Conf]
    
14. Wai-Kei Mak, Evangeline F. Y. Young
    Temporal logic replication for dynamically reconfigurable FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:190-195 [Conf]
    
15. Hao Li, Wai-Kei Mak, Srinivas Katkoori
    Force-Directed Performance-Driven Placement Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:193-198 [Conf]
    
16. Wai-Kei Mak, D. F. Wong
    A fast hypergraph min-cut algorithm for circuit partitioning. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:30, n:1, pp:1-11 [Journal]
    
17. Wai-Kei Mak, David P. Morton, R. Kevin Wood
    Monte Carlo bounding techniques for determining solution quality in stochastic programs. [Citation Graph (0, 0)][DBLP]
    Oper. Res. Lett., 1999, v:24, n:1-2, pp:47-56 [Journal]
    
18. Wai-Kei Mak
    Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:491-497 [Journal]
    
19. Wai-Kei Mak
    I/O placement for FPGAs with multiple I/O standards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:315-321 [Journal]
    
20. Wai-Kei Mak, Martin D. F. Wong
    On optimal board-level routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:282-289 [Journal]
    
21. Wai-Kei Mak, Martin D. F. Wong
    Minimum replication min-cut partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1221-1227 [Journal]
    
22. Wai-Kei Mak, Evangeline F. Y. Young
    Temporal logic replication for dynamically reconfigurable FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:952-959 [Journal]
    
23. Hao Li, Srinivas Katkoori, Wai-Kei Mak
    Power minimization algorithms for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:1, pp:33-51 [Journal]
    
24. Wai-Kei Mak, D. F. Wong
    Board-level multiterminal net routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:151-167 [Journal]
    
25. 
    Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. [Citation Graph (, )][DBLP]
    
    
26. 
    Voltage Island Generation under Performance Requirement for SoC Designs. [Citation Graph (, )][DBLP]
    
    
27. 
    Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. [Citation Graph (, )][DBLP]
    
    
28. 
    How to consider shorts and guarantee yield rate improvement for redundant wire insertion. [Citation Graph (, )][DBLP]
    
    
29. 
    Pad assignment for die-stacking System-in-Package design. [Citation Graph (, )][DBLP]
    
    
30. 
    SafeChoice: a novel clustering algorithm for wirelength-driven placement. [Citation Graph (, )][DBLP]
    
    
31. 
    FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (, )][DBLP]
    
    
32. 
    Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. [Citation Graph (, )][DBLP]