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Publications of Author

1. Wei Chen, Massoud Pedram, Premal Buch
   Buffered Routing Tree Construction Under Buffer Placement Blockages. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:381-386 [Conf]
   
2. John Lillis, Premal Buch
   Table-Lookup Methods for Improved Performance-Driven Routing. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:368-373 [Conf]
   
3. Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan
   DFM rules! [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:168-169 [Conf]
   
4. Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
   Logic synthesis for large pass transistor circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1997, pp:663-670 [Conf]
   
5. Premal Buch, Christopher K. Lennard, A. Richard Newton
   Engineering change for power optimization using global sensitivity and synthesis flexibility. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1997, pp:88-91 [Conf]
   
6. Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh
   Techniques for fast circuit simulation applied to power estimation of CMOS circuits. [Citation Graph (0, 0)][DBLP]
   ISLPD, 1995, pp:135-138 [Conf]
   
7. Christopher K. Lennard, Premal Buch, A. Richard Newton
   Logic synthesis using power-sensitive don't care sets. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1996, pp:293-296 [Conf]
   
8. Premal Buch, Ernest S. Kuh
   SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1997, pp:403-407 [Conf]
   
9. Wei Chen, Massoud Pedram, Premal Buch
   Buffered Routing Tree Construction under Buffer Placement Blockages. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:381-386 [Conf]