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Yiran Chen :
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Yiran Chen , Kaushik Roy , Cheng-Kok Koh Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:893-898 [Conf ] Hai Li , Yiran Chen , Kaushik Roy , Cheng-Kok Koh SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:158-163 [Conf ] Yiran Chen , Venkataramanan Balakrishnan , Cheng-Kok Koh , Kaushik Roy Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:931-937 [Conf ] Hai Li , Swarup Bhunia , Yiran Chen , T. N. Vijaykumar , Kaushik Roy Deterministic Clock Gating for Microprocessor Power Reduction. [Citation Graph (0, 0)][DBLP ] HPCA, 2003, pp:113-0 [Conf ] Wai-Ching Douglas Lam , J. Jam , Cheng-Kok Koh , Venkataramanan Balakrishnan , Yiran Chen Statistical based link insertion for robust clock network design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:588-591 [Conf ] Yiran Chen , Hai Li , Kaushik Roy , Cheng-Kok Koh Cascaded carry-select adder (C2 SA): a new structure for low-power CSA design. [Citation Graph (0, 0)][DBLP ] ISLPED, 2005, pp:115-118 [Conf ] Yiran Chen , Kaushik Roy , Cheng-Kok Koh Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:229-234 [Conf ] Dongku Kang , Yiran Chen , Kaushik Roy Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:48-53 [Conf ] Hong Li , Cheng-Kok Koh , Venkataramanan Balakrishnan , Yiran Chen Statistical Timing Analysis Considering Spatial Correlations. [Citation Graph (0, 0)][DBLP ] ISQED, 2007, pp:102-107 [Conf ] Yiran Chen , Kaushik Roy , Cheng-Kok Koh Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:75-85 [Journal ] Hai Li , Swarup Bhunia , Yiran Chen , Kaushik Roy , T. N. Vijaykumar DCG: deterministic clock-gating for low-power microprocessor design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:245-254 [Journal ] Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. [Citation Graph (, )][DBLP ] Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. [Citation Graph (, )][DBLP ] Impact of process variations on emerging memristor. [Citation Graph (, )][DBLP ] An overview of non-volatile memory technology and the implication for tools and architectures. [Citation Graph (, )][DBLP ] Spintronic memristor devices and application. [Citation Graph (, )][DBLP ] A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM). [Citation Graph (, )][DBLP ] A novel architecture of the 3D stacked MRAM L2 cache for CMPs. [Citation Graph (, )][DBLP ] VOSCH: Voltage scaled cache hierarchies. [Citation Graph (, )][DBLP ] Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. [Citation Graph (, )][DBLP ] Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. [Citation Graph (, )][DBLP ] Low-power dual-element memristor based memory design. [Citation Graph (, )][DBLP ] Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. [Citation Graph (, )][DBLP ] Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). [Citation Graph (, )][DBLP ] Scalability of PCMO-based resistive switch device in DSM technologies. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.006secs