The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Chi-Ying Tsui: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chun-hong Chen, Chi-Ying Tsui
    Timing Optimization of Logic Network Using Gate Duplication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:233-236 [Conf]
  2. Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui
    A dual--band switching digital controller for a buck converter. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:561-562 [Conf]
  3. Yat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui
    Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:102-103 [Conf]
  4. Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui
    Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:104-105 [Conf]
  5. Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S. Cheng
    VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:3-4 [Conf]
  6. Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
    Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:647-652 [Conf]
  7. Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
    Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:663-665 [Conf]
  8. Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui
    Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:539-540 [Conf]
  9. Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok
    A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:19-20 [Conf]
  10. Massoud Pedram, Chi-Ying Tsui, Qing Wu
    An Integrated Battery-Hardware Model for Portable Electronics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:109-0 [Conf]
  11. Chi-Ying Tsui, Louis Chung-Yin Kwan, Chin-Tau Lea
    VLSI implementation of a switch fabric for mixed ATM and IP traffic. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:5-6 [Conf]
  12. Chi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su
    Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:96-97 [Conf]
  13. Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow
    Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:125-130 [Conf]
  14. Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
    Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1994, pp:489-498 [Conf]
  15. Lap-Fai Leung, Chi-Ying Tsui
    Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:833-838 [Conf]
  16. Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain
    Application-Driven Design Automation for Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:512-517 [Conf]
  17. Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram
    A Power Estimation Framework for Designing Low Power Portable Video Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:421-424 [Conf]
  18. Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram
    Improving the Efficiency of Power Simulators by Input Vector Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:165-168 [Conf]
  19. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Technology Decomposition and Mapping Targeting Low Power Dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:68-73 [Conf]
  20. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:18-23 [Conf]
  21. Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
    Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:634-639 [Conf]
  22. Siu-Kei Wong, Chi-Ying Tsui
    Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:130-135 [Conf]
  23. Feng Liu, Chi-Ying Tsui
    Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:81-86 [Conf]
  24. Feng Liu, Chi-Ying Tsui
    A Data Discarding Framework for Reducing the Energy Consumption of Viterbi Decoder in Decoding Broadcasted Wireless Multi-Resolution JPEG2000 Images. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:21-26 [Conf]
  25. Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
    Low power state assignment targeting two-and multi-level logic implementations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:82-87 [Conf]
  26. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Efficient estimation of dynamic power consumption under a real delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:224-228 [Conf]
  27. Yi-Ching Au, Chi-Ying Tsui
    Least leakage vector assisted technology mapping for total power optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:145-148 [Conf]
  28. Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui
    Design and implementation of high-speed arbiter for large scale VOQ crossbar switches. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:308-311 [Conf]
  29. Wing-Hung Ki, Feng Su, Chi-Ying Tsui
    Charge redistribution loss consideration in optimal charge pump design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1895-1898 [Conf]
  30. Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok
    Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:447-450 [Conf]
  31. Hing-mo Lam, Chi-Ying Tsui
    High performance and low power completion detection circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:405-408 [Conf]
  32. Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
    Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:309-312 [Conf]
  33. Feng Su, Wing-Hung Ki, Chi-Ying Tsui
    Gate control strategies for high efficiency charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1907-1910 [Conf]
  34. Dongsheng Ma, Wing-Hung Ki, Philip K. T. Mok, Chi-Ying Tsui
    Single-inductor multiple-output switching converters with bipolar outputs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:301-304 [Conf]
  35. Wai-Kwong Lee, Chi-Ying Tsui
    Finite state machine partitioning for low power. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:306-309 [Conf]
  36. Chi-Ying Tsui, R. S.-K. Cheng, C. Ling
    Low power ACS unit design for the Viterbi decoder [CDMA wireless systems]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:137-140 [Conf]
  37. Chi Wai Yung, Hung Fai Fu, Chi-Ying Tsui, Roger S. Cheng, D. George
    Unequal error protection for wireless transmission of MPEG audio. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:342-345 [Conf]
  38. Siu-Kei Wong, Chi-Ying Tsui
    Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:321-324 [Conf]
  39. Yan Wang, Hing Mo Lam, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow
    Low complexity OFDM receiver using Log-FFT for coded OFDM system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:445-448 [Conf]
  40. Kwan-wai Wong, Chi-Ying Tsui, R. S.-K. Cheng, Wai Ho Mow
    A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:273-276 [Conf]
  41. Chun-hong Chen, Chi-Ying Tsui
    Towards the capability of providing power-area-delay trade-off at the register transfer level. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:24-29 [Conf]
  42. Zhong-Li He, Kai-Keung Chan, Chi-Ying Tsui, Ming L. Liou
    Low power motion estimation design using adaptive pixel truncation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:167-172 [Conf]
  43. Oliver Yuk-Hang Leung, Chung-Wai Yue, Chi-Ying Tsui, Roger S. Cheng
    Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:36-41 [Conf]
  44. Jie Jin, Chi-Ying Tsui
    A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:406-411 [Conf]
  45. Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
    Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:553-563 [Conf]
  46. Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao
    A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:830-835 [Conf]
  47. Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
    Saving Power in the Control Path of Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:24-30 [Journal]
  48. Chi-Ying Tsui, Massoud Pedram
    Accurate and efficient power simulation strategy by compacting the input vector set. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:25, n:1, pp:37-52 [Journal]
  49. Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
    Gate-level power estimation using tagged probabilistic simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1099-1107 [Journal]
  50. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Power efficient technology decomposition and mapping under an extended power consumption model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1110-1122 [Journal]
  51. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Low-power state assignment targeting two- and multilevel logic implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1281-1291 [Journal]
  52. Zhong-Li He, Chi-Ying Tsui, Kai-Keung Chan, Ming L. Liou
    Low-power VLSI design for motion estimation using adaptive pixel truncation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:5, pp:669-678 [Journal]
  53. Lap-Fai Leung, Chi-Ying Tsui
    Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:128-131 [Conf]
  54. Lu Chao, Chi-Ying Tsui, Wing-Hung Ki
    A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1349-1352 [Conf]
  55. Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
    An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1353-1356 [Conf]
  56. Hing-mo Lam, Chi-Ying Tsui
    High performance single clock cycle CMOS comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  57. Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
    A charge based computation system and control strategy for energy harvesting applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  58. Feng Su, Wing-Hung Ki, Chi-Ying Tsui
    High efficiency cross-coupled doubler with no reversion loss. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  59. Feng Liu, Chi-Ying Tsui
    Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  60. Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
    Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  61. Jie Jin, Chi-Ying Tsui
    Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1172-1176 [Journal]
  62. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Power estimation methods for sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:404-416 [Journal]
  63. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:495- [Journal]
  64. Oliver Yuk-Hang Leung, Chi-Ying Tsui, R. S.-K. Cheng
    Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:34-41 [Journal]

  65. Low energy level converter design for sub-Vth logics. [Citation Graph (, )][DBLP]


  66. An inductor-less MPPT design for light energy harvesting systems. [Citation Graph (, )][DBLP]


  67. Threshold Voltage Start-up Boost Converter for Sub-mA Applications. [Citation Graph (, )][DBLP]


  68. Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches. [Citation Graph (, )][DBLP]


  69. A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems. [Citation Graph (, )][DBLP]


  70. An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting. [Citation Graph (, )][DBLP]


  71. Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications. [Citation Graph (, )][DBLP]


  72. Vibration energy scavenging and management for ultra low power applications. [Citation Graph (, )][DBLP]


  73. A micro power management system and maximum output power control for solar energy harvesting applications. [Citation Graph (, )][DBLP]


  74. A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes. [Citation Graph (, )][DBLP]


  75. A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications. [Citation Graph (, )][DBLP]


  76. A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. [Citation Graph (, )][DBLP]


  77. Low Complexity SST Viterbi Decoder. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.010secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002