SCEAS

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Kuo-Hsing Cheng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Kuo-Hsing Cheng, Shun-Wen Cheng
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2002, pp:155-159 [Conf]
Kuo-Hsing Cheng, Yu-lung Lo
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. [Citation Graph (0, 0)][DBLP]
DATE Designers' Forum, 2006, pp:178-182 [Conf]
Kuo-Hsing Cheng, Yu-lung Lo
A fast-lock DLL with power-on reset circuit. [Citation Graph (0, 0)][DBLP]
ISCAS (4), 2004, pp:357-360 [Conf]
Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. [Citation Graph (0, 0)][DBLP]
ISCAS (2), 2005, pp:1174-1177 [Conf]
Kuo-Hsing Cheng, Tsung-Shen Chen, Chia Ming Tu
A 14-bit, 200 MS/s digital-to-analog converter without trimming. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2004, pp:353-358 [Conf]
Kuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei
A CMOS charge pump for sub-2.0 V operation. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2003, pp:89-92 [Conf]
Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen
BIST for clock jitter measurements. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2003, pp:577-580 [Conf]
Kuo-Hsing Cheng, Yung-Hsiang Lin
A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2003, pp:425-428 [Conf]
Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang
A new robust handshake for asymmetric asynchronous micro-pipelines. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2003, pp:209-212 [Conf]
Kuo-Hsing Cheng, Yu-lung Lo, Wen Fang Yu
A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. [Citation Graph (0, 0)][DBLP]
ISCAS (2), 2003, pp:196-199 [Conf]
Kuo-Hsing Cheng, Chen-Lung Wu, Yu-lung Lo, Chia-Wei Su
A phase-detect synchronous mirror delay for clock skew-compensation circuits. [Citation Graph (0, 0)][DBLP]
ISCAS (2), 2005, pp:1070-1073 [Conf]
Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2004, pp:777-780 [Conf]
Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. [Citation Graph (0, 0)][DBLP]
ISCAS, 1995, pp:1572-1575 [Conf]
Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. [Citation Graph (0, 0)][DBLP]
ISCAS, 1994, pp:23-26 [Conf]
Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications. [Citation Graph (0, 0)][DBLP]
ISCAS, 1995, pp:25-28 [Conf]
Shun-Wen Cheng, Kuo-Hsing Cheng
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2001, pp:167-170 [Conf]
Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung
A low-power high driving ability voltage control oscillator used in PLL. [Citation Graph (0, 0)][DBLP]
ISCAS (4), 2001, pp:614-617 [Conf]
Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang
Static divided word matching line for low-power Content Addressable Memory design. [Citation Graph (0, 0)][DBLP]
ISCAS (2), 2004, pp:629-632 [Conf]
Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. [Citation Graph (0, 0)][DBLP]
ISVLSI, 2004, pp:233-236 [Conf]
Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. [Citation Graph (0, 0)][DBLP]
IWSOC, 2004, pp:65-68 [Conf]
Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu
A Robust Handshake for Asynchronous System. [Citation Graph (0, 0)][DBLP]
IWSOC, 2003, pp:16-19 [Conf]
Kuo-Hsing Cheng, Yu-lung Lo, Wen Fang Yu, Shu-Yin Hung
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. [Citation Graph (0, 0)][DBLP]
IWSOC, 2003, pp:90-93 [Conf]
Kuo-Hsing Cheng, Shun-Wen Cheng
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2002, pp:155-159 [Conf]
Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics. [Citation Graph (0, 0)][DBLP]
Journal of Circuits, Systems, and Computers, 2006, v:15, n:1, pp:13-28 [Journal]
Kuo-Hsing Cheng, Shun-Wen Cheng
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. [Citation Graph (0, 0)][DBLP]
J. Inf. Sci. Eng., 2006, v:22, n:4, pp:975-989 [Journal]
Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su
A Sub-1V Low-Power High-Speed Static Frequency Divider. [Citation Graph (0, 0)][DBLP]
ISCAS, 2007, pp:3848-3851 [Conf]
Kuo-Hsing Cheng, Kai-Fei Chang, Yu-lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng
A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. [Citation Graph (0, 0)][DBLP]
ISCAS, 2006, pp:- [Conf]
Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang
Self-sampled vernier delay line for built-in clock jitter measurement. [Citation Graph (0, 0)][DBLP]
ISCAS, 2006, pp:- [Conf]
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. [Citation Graph (, )][DBLP]
0.5V 160-MHz 260uW all digital phase-locked loop. [Citation Graph (, )][DBLP]

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