Search the dblp DataBase

Publications of Author

1. Lei Cheng, Liang Deng, Martin D. F. Wong
   Floorplanning for 3-D VLSI design. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:405-411 [Conf]
   
2. Liang Deng, Martin D. F. Wong
   An exact algorithm for the statistical shortest path problem. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:965-970 [Conf]
   
3. Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong
   A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:117-120 [Conf]
   
4. Liang Deng, Martin D. F. Wong
   Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1104-1109 [Conf]
   
5. Liang Deng, Martin D. F. Wong
   Energy optimization in memory address bus structure for application-specific systems. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:232-237 [Conf]
   
6. Liang Deng, Martin D. F. Wong
   Buffer insertion under process variations for delay minimization. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:317-321 [Conf]
   
7. Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
   OPC-Friendly Bus Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:847-852 [Conf]
   
8. Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
   Dummy fill density analysis with coupling constraints. [Citation Graph (0, 0)][DBLP]
   ISPD, 2007, pp:3-10 [Conf]
   
9. 
   Fast and Accurate OPC for Standard-Cell Layouts. [Citation Graph (, )][DBLP]
   
   
10. 
    Coupling-aware Dummy Metal Insertion for Lithography. [Citation Graph (, )][DBLP]
    
    
11. 
    Wire shaping is practical. [Citation Graph (, )][DBLP]