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Author:
Martin D. F. Wong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lei Cheng, Liang Deng, Martin D. F. Wong
    Floorplanning for 3-D VLSI design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:405-411 [Conf]
  2. Yongseok Cheon, Martin D. F. Wong
    Crowdedness-balanced multilevel partitioning for uniform resource utilization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:418-423 [Conf]
  3. Liang Deng, Martin D. F. Wong
    An exact algorithm for the statistical shortest path problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:965-970 [Conf]
  4. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
    Optimal redistribution of white space for wire length minimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:412-417 [Conf]
  5. Xiaoping Tang, Martin D. F. Wong
    On handling arbitrary rectilinear shape constraint. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:38-41 [Conf]
  6. Xiaoping Tang, Martin D. F. Wong
    Tradeoff routing resource, runtime and quality in buffered routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:430-433 [Conf]
  7. Sebastian Vogel, Martin D. F. Wong
    Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:315-319 [Conf]
  8. Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
    Redundant-via enhanced maze routing for yield improvement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1148-1151 [Conf]
  9. Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong
    CMP aware shuttle mask floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1111-1114 [Conf]
  10. Esra Erdem, Vladimir Lifschitz, Martin D. F. Wong
    Wire Routing and Satisfiability Planning. [Citation Graph (0, 0)][DBLP]
    Computational Logic, 2000, pp:822-836 [Conf]
  11. Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong
    A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:117-120 [Conf]
  12. Li-Da Huang, Martin D. F. Wong
    Optical proximity correction (OPC): friendly maze routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:186-191 [Conf]
  13. Huaizhi Wu, Martin D. F. Wong, I-Min Liu
    Timing-constrained and voltage-island-aware voltage assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:429-432 [Conf]
  14. Liang Deng, Martin D. F. Wong
    Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1104-1109 [Conf]
  15. Liang Deng, Martin D. F. Wong
    Energy optimization in memory address bus structure for application-specific systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:232-237 [Conf]
  16. Lei Cheng, Martin D. F. Wong
    Floorplan design for multi-million gate FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:292-299 [Conf]
  17. Yongseok Cheon, Seokjin Lee, Martin D. F. Wong
    Stable Multiway Circuit Partitioning for ECO. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:718-725 [Conf]
  18. Liang Deng, Martin D. F. Wong
    Buffer insertion under process variations for delay minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:317-321 [Conf]
  19. Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
    A Min-Cost Flow Based Detailed Router for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:388-393 [Conf]
  20. Muhammet Mustafa Ozdal, Martin D. F. Wong
    Length-Matching Routing for High-Speed Printed Circuit Boards. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:394-400 [Conf]
  21. Muhammet Mustafa Ozdal, Martin D. F. Wong
    Simultaneous escape routing and layer assignment for dense PCBs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:822-829 [Conf]
  22. Muhammet Mustafa Ozdal, Martin D. F. Wong
    A provably good algorithm for high performance bus routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:830-837 [Conf]
  23. Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger
    An escape routing framework for dense boards with high-speed design constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:759-766 [Conf]
  24. Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger
    Optimal routing algorithms for pin clusters in high-density multichip modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:767-774 [Conf]
  25. Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang
    Post-placement voltage island generation under performance requirement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:309-316 [Conf]
  26. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Bus-Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:66-73 [Conf]
  27. Yu Zhong, Martin D. F. Wong
    Fast algorithms for IR drop analysis in large power grid. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:351-357 [Conf]
  28. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
    I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:562-567 [Conf]
  29. Muhammet Mustafa Ozdal, Martin D. F. Wong
    A Two-Layer Bus Routing Algorithm for High-Speed Boards. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:99-105 [Conf]
  30. Martin D. F. Wong
    Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:106-110 [Conf]
  31. Esra Erdem, Martin D. F. Wong
    Rectilinear Steiner Tree Construction Using Answer Set Programming. [Citation Graph (0, 0)][DBLP]
    ICLP, 2004, pp:386-399 [Conf]
  32. Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee
    Explicit gate delay model for timing evaluation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:32-38 [Conf]
  33. Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong
    Current Calculation on VLSI Signal Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:580-585 [Conf]
  34. Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
    Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:181-186 [Conf]
  35. Hua Xiang, I-Min Liu, Martin D. F. Wong
    Wire Planning with Bounded Over-the-Block Wires. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:622-627 [Conf]
  36. Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
    OPC-Friendly Bus Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:847-852 [Conf]
  37. Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong
    IR Drop and Ground Bounce Awareness Timing Model. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:226-231 [Conf]
  38. Yang Cai, Martin D. F. Wong
    Optimal channel pin assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1413-1424 [Journal]
  39. Yang Cai, Martin D. F. Wong
    Channel/switchbox definition for VLSI building-block layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1485-1493 [Journal]
  40. Yang Cai, Martin D. F. Wong
    On minimizing the number of L-shaped channels in building-block layout [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:757-769 [Journal]
  41. Yang Cai, Martin D. F. Wong
    Efficient via shifting algorithms in channel compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1848-1857 [Journal]
  42. Yang Cai, Martin D. F. Wong
    On shifting blocks and terminals to minimize channel density. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:178-186 [Journal]
  43. Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong
    Matching-based algorithm for FPGA channel segmentation design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:784-791 [Journal]
  44. Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong
    Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1014-1025 [Journal]
  45. Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
    Simultaneous power supply planning and noise avoidance in floorplan design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:578-587 [Journal]
  46. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong
    I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2552-2556 [Journal]
  47. Yongseok Cheon, Martin D. F. Wong
    Design hierarchy-guided multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:420-427 [Journal]
  48. Chris C. N. Chu, Martin D. F. Wong
    A matrix synthesis approach to thermal placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1166-1174 [Journal]
  49. Chris C. N. Chu, Martin D. F. Wong
    Greedy wire-sizing is linear time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:398-405 [Journal]
  50. Chris C. N. Chu, Martin D. F. Wong
    A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:787-798 [Journal]
  51. Chris C. N. Chu, Martin D. F. Wong
    An efficient and optimal algorithm for simultaneous buffer and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1297-1304 [Journal]
  52. Jason Cong, Martin D. F. Wong, C. L. Liu
    A new approach to three- or four-layer channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1094-1104 [Journal]
  53. Youxin Gao, Martin D. F. Wong
    Optimal shape function for a bidirectional wire under Elmore delay model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:994-999 [Journal]
  54. Youxin Gao, Martin D. F. Wong
    Wire-sizing optimization with inductance consideration using transmission-line model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1759-1767 [Journal]
  55. Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell
    Topological channel routing [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1177-1197 [Journal]
  56. Mohankumar Guruswamy, Martin D. F. Wong
    Echelon: a multilayer detailed area router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1126-1136 [Journal]
  57. T. W. Her, Martin D. F. Wong
    On over-the-cell channel routing with cell orientations consideration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:766-772 [Journal]
  58. T. W. Her, Martin D. F. Wong
    Module implementation selection and its application to transistor placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:645-651 [Journal]
  59. T. W. Her, Ting-Chi Wang, Martin D. F. Wong
    Performance-driven channel pin assignment algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:849-857 [Journal]
  60. Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao
    Maze routing with buffer insertion under transition time constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:91-95 [Journal]
  61. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
    A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:141-147 [Journal]
  62. Glenn G. Lai, Donald S. Fussell, Martin D. F. Wong
    Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:317-324 [Journal]
  63. Minghorng Lai, Martin D. F. Wong
    Maze routing with buffer insertion and wiresizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1205-1209 [Journal]
  64. Seokjin Lee, Martin D. F. Wong
    Timing-driven routing for FPGAs based on Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:506-510 [Journal]
  65. Huiqun Liu, Martin D. F. Wong
    Network-flow-based multiway partitioning with area and pin constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:50-59 [Journal]
  66. Wai-Kei Mak, Martin D. F. Wong
    On optimal board-level routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:282-289 [Journal]
  67. Wai-Kei Mak, Martin D. F. Wong
    Minimum replication min-cut partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1221-1227 [Journal]
  68. Muhammet Mustafa Ozdal, Martin D. F. Wong
    Algorithmic study of single-layer bus routing for high-speed boards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:490-503 [Journal]
  69. Muhammet Mustafa Ozdal, Martin D. F. Wong
    Algorithms for simultaneous escape routing and Layer assignment of dense PCBs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1510-1522 [Journal]
  70. Rajmohan Rajaraman, Martin D. F. Wong
    Optimum clustering for delay minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1490-1495 [Journal]
  71. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
    Fast evaluation of sequence pair in block placement by longestcommon subsequence computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1406-1413 [Journal]
  72. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
    Minimizing wire length in floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1744-1753 [Journal]
  73. Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan
    Algorithms for an FPGA switch module routing problem with application to global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:32-46 [Journal]
  74. Khe-Sing The, Martin D. F. Wong, Jason Cong
    A layout modification approach to via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:536-541 [Journal]
  75. Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong
    Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:63-71 [Journal]
  76. Ruiqi Tian, Martin D. F. Wong, Robert Boone
    Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:902-910 [Journal]
  77. Ting-Chi Wang, Martin D. F. Wong
    Optimal floorplan area optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:992-1002 [Journal]
  78. Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong
    Optimal net assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:265-269 [Journal]
  79. Martin D. F. Wong, Mohankumar Guruswamy
    Channel ordering for VLSI layout with rectilinear modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1425-1431 [Journal]
  80. Martin D. F. Wong, Dwight D. Hill
    Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:173-174 [Journal]
  81. Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
    An ECO routing algorithm for eliminating coupling-capacitance violations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1754-1762 [Journal]
  82. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Min-cost flow-based algorithm for simultaneous pin assignment and routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:870-878 [Journal]
  83. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Bus-driven floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1522-1530 [Journal]
  84. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    Slicing floorplans with range constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:272-278 [Journal]
  85. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:800-807 [Journal]
  86. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    Slicing floorplans with boundary constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1385-1389 [Journal]
  87. Hannah Honghua Yang, Martin D. F. Wong
    Balanced partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1533-1540 [Journal]
  88. Hannah Honghua Yang, Martin D. F. Wong
    Circuit clustering for delay minimization under area and pin constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:976-986 [Journal]
  89. Hannah Honghua Yang, Martin D. F. Wong
    Optimal min-area min-cut replication in partitioned circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1175-1183 [Journal]
  90. Hai Zhou, Martin D. F. Wong
    Global routing with crosstalk constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1683-1688 [Journal]
  91. Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous routing and buffer insertion with restrictions onbuffer locations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:819-824 [Journal]
  92. Kai Zhu, Martin D. F. Wong
    Clock skew minimization during FPGA placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:4, pp:376-385 [Journal]
  93. Kai Zhu, Martin D. F. Wong
    Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:316-323 [Journal]
  94. Muhammet Mustafa Ozdal, Martin D. F. Wong
    Two-layer bus routing for high-speed printed circuit boards. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:213-227 [Journal]
  95. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:561-572 [Journal]
  96. Huaizhi Wu, Martin D. F. Wong
    Improving Voltage Assignment by Outlier Detection and Incremental Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:459-464 [Conf]
  97. Lei Cheng, Deming Chen, Martin D. F. Wong
    DDBDD: Delay-Driven BDD Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:910-915 [Conf]
  98. Lei Cheng, Deming Chen, Martin D. F. Wong
    GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:318-323 [Conf]
  99. Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
    Is your layout density verification exact?: a fast exact algorithm for density calculation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:19-26 [Conf]
  100. Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
    Dummy fill density analysis with coupling constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:3-10 [Conf]

  101. On using SAT to ordered escape problems. [Citation Graph (, )][DBLP]


  102. Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid. [Citation Graph (, )][DBLP]


  103. Fast and Accurate OPC for Standard-Cell Layouts. [Citation Graph (, )][DBLP]


  104. Fast Placement Optimization of Power Supply Pads. [Citation Graph (, )][DBLP]


  105. Coupling-aware Dummy Metal Insertion for Lithography. [Citation Graph (, )][DBLP]


  106. Ordered escape routing based on Boolean satisfiability. [Citation Graph (, )][DBLP]


  107. Thermal-driven analog placement considering device matching. [Citation Graph (, )][DBLP]


  108. Automatic bus planner for dense PCBs. [Citation Graph (, )][DBLP]


  109. Flip-chip routing with unified area-I/O pad assignments for package-board co-design. [Citation Graph (, )][DBLP]


  110. A correct network flow model for escape routing. [Citation Graph (, )][DBLP]


  111. An effective GPU implementation of breadth-first search. [Citation Graph (, )][DBLP]


  112. An optimal algorithm for finding disjoint rectangles and its application to PCB routing. [Citation Graph (, )][DBLP]


  113. Efficient ASIP design for configurable processors with fine-grained resource sharing. [Citation Graph (, )][DBLP]


  114. Optimal bus sequencing for escape routing in dense PCBs. [Citation Graph (, )][DBLP]


  115. Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. [Citation Graph (, )][DBLP]


  116. Untangling twisted nets for bus routing. [Citation Graph (, )][DBLP]


  117. Archer: a history-driven global routing algorithm. [Citation Graph (, )][DBLP]


  118. BSG-Route: a length-matching router for general topology. [Citation Graph (, )][DBLP]


  119. Optimal layer assignment for escape routing of buses. [Citation Graph (, )][DBLP]


  120. A routing approach to reduce glitches in low power FPGAs. [Citation Graph (, )][DBLP]


  121. Wire shaping is practical. [Citation Graph (, )][DBLP]


  122. B-escape: a simultaneous escape routing algorithm based on boundary routing. [Citation Graph (, )][DBLP]


  123. Thermal-Aware IR Drop Analysis in Large Power Grid. [Citation Graph (, )][DBLP]


  124. Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid. [Citation Graph (, )][DBLP]


  125. A negotiated congestion based router for simultaneous escape routing. [Citation Graph (, )][DBLP]


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