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Bao Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
    Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:527-532 [Conf]
  2. Andrew B. Kahng, Bao Liu, Xu Xu
    Statistical gate delay calculation with crosstalk alignment consideration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:223-228 [Conf]
  3. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:408-0 [Conf]
  4. Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
    Non-tree routing for reliability and yield improvement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:260-266 [Conf]
  5. Andrew B. Kahng, Bao Liu, Qinke Wang
    Supply Voltage Degradation Aware Analytical Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:437-443 [Conf]
  6. Bao Liu, Lihong Ren, Yongsheng Ding
    A Novel Intelligent Controller Based on Modulation of Neuroendocrine System. [Citation Graph (0, 0)][DBLP]
    ISNN (3), 2005, pp:119-124 [Conf]
  7. Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
    Efficient decoupling capacitor planning via convex programming methods. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:102-107 [Conf]
  8. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  9. Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
    SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:638-643 [Conf]
  10. Andrew B. Kahng, Bao Liu, Xu Xu
    Constructing Current-Based Gate Models Based on Existing Timing Library. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:37-42 [Conf]
  11. Bao Liu
    Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:257-262 [Conf]
  12. Andrew B. Kahng, Bao Liu
    Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:183-188 [Conf]
  13. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
    Interconnect implications of growth-based structural models for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:99-106 [Conf]
  14. Andrew B. Kahng, Bao Liu, Xu Xu
    Statistical crosstalk aggressor alignment aware interconnect delay calculation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:91-97 [Conf]
  15. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum buffered routing with bounded capacitive load for slew rate and reliability control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:241-253 [Journal]
  16. Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    On the skew-bounded minimum-buffer routing tree problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:937-945 [Journal]
  17. Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
    Nontree routing for reliability and yield improvement [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:148-156 [Journal]
  18. Bao Liu, Sheldon X.-D. Tan
    Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1284-1287 [Journal]
  19. Andrew B. Kahng, Bao Liu, Qinke Wang
    Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:904-912 [Journal]
  20. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
    Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:177-189 [Journal]

  21. Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. [Citation Graph (, )][DBLP]


  22. A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. [Citation Graph (, )][DBLP]


  23. Signal Probability Based Statistical Timing Analysis. [Citation Graph (, )][DBLP]


  24. Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. [Citation Graph (, )][DBLP]


  25. A collaborative optimized genetic algorithm based on regulation mechanism of neuroendocrine-immune system. [Citation Graph (, )][DBLP]


  26. Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. [Citation Graph (, )][DBLP]


  27. Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. [Citation Graph (, )][DBLP]


  28. Robust differential asynchronous nanoelectronic circuits. [Citation Graph (, )][DBLP]


  29. Energy Efficient Swing signal generation circuits for clock distribution networks. [Citation Graph (, )][DBLP]


  30. A Voltage Controlled Nano Addressing Circuit. [Citation Graph (, )][DBLP]


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