Search the dblp DataBase
Bao Liu :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Chung-Kuan Cheng , Andrew B. Kahng , Bao Liu , Dirk Stroobandt Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2001, pp:527-532 [Conf ] Andrew B. Kahng , Bao Liu , Xu Xu Statistical gate delay calculation with crosstalk alignment consideration. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:223-228 [Conf ] Charles J. Alpert , Andrew B. Kahng , Bao Liu , Ion I. Mandoiu , Alexander Zelikovsky Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:408-0 [Conf ] Andrew B. Kahng , Bao Liu , Ion I. Mandoiu Non-tree routing for reliability and yield improvement. [Citation Graph (0, 0)][DBLP ] ICCAD, 2002, pp:260-266 [Conf ] Andrew B. Kahng , Bao Liu , Qinke Wang Supply Voltage Degradation Aware Analytical Placement. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:437-443 [Conf ] Bao Liu , Lihong Ren , Yongsheng Ding A Novel Intelligent Controller Based on Modulation of Neuroendocrine System. [Citation Graph (0, 0)][DBLP ] ISNN (3), 2005, pp:119-124 [Conf ] Andrew B. Kahng , Bao Liu , Sheldon X.-D. Tan Efficient decoupling capacitor planning via convex programming methods. [Citation Graph (0, 0)][DBLP ] ISPD, 2006, pp:102-107 [Conf ] Charles J. Alpert , Milos Hrkic , Jiang Hu , Andrew B. Kahng , John Lillis , Bao Liu , Stephen T. Quay , Sachin S. Sapatnekar , A. J. Sullivan , Paul Villarrubia Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP ] ISPD, 2001, pp:4-9 [Conf ] Andrew B. Kahng , Bao Liu , Sheldon X.-D. Tan SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:638-643 [Conf ] Andrew B. Kahng , Bao Liu , Xu Xu Constructing Current-Based Gate Models Based on Existing Timing Library. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:37-42 [Conf ] Bao Liu Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations. [Citation Graph (0, 0)][DBLP ] ISQED, 2007, pp:257-262 [Conf ] Andrew B. Kahng , Bao Liu Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2003, pp:183-188 [Conf ] Chung-Kuan Cheng , Andrew B. Kahng , Bao Liu Interconnect implications of growth-based structural models for VLSI circuits. [Citation Graph (0, 0)][DBLP ] SLIP, 2001, pp:99-106 [Conf ] Andrew B. Kahng , Bao Liu , Xu Xu Statistical crosstalk aggressor alignment aware interconnect delay calculation. [Citation Graph (0, 0)][DBLP ] SLIP, 2006, pp:91-97 [Conf ] Charles J. Alpert , Andrew B. Kahng , Bao Liu , Ion I. Mandoiu , Alexander Zelikovsky Minimum buffered routing with bounded capacitive load for slew rate and reliability control. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:241-253 [Journal ] Christoph Albrecht , Andrew B. Kahng , Bao Liu , Ion I. Mandoiu , Alexander Zelikovsky On the skew-bounded minimum-buffer routing tree problem. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:937-945 [Journal ] Andrew B. Kahng , Bao Liu , Ion I. Mandoiu Nontree routing for reliability and yield improvement [IC layout]. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:148-156 [Journal ] Bao Liu , Sheldon X.-D. Tan Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1284-1287 [Journal ] Andrew B. Kahng , Bao Liu , Qinke Wang Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:904-912 [Journal ] Chung-Kuan Cheng , Andrew B. Kahng , Bao Liu , Dirk Stroobandt Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:177-189 [Journal ] Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. [Citation Graph (, )][DBLP ] A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. [Citation Graph (, )][DBLP ] Signal Probability Based Statistical Timing Analysis. [Citation Graph (, )][DBLP ] Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. [Citation Graph (, )][DBLP ] A collaborative optimized genetic algorithm based on regulation mechanism of neuroendocrine-immune system. [Citation Graph (, )][DBLP ] Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. [Citation Graph (, )][DBLP ] Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. [Citation Graph (, )][DBLP ] Robust differential asynchronous nanoelectronic circuits. [Citation Graph (, )][DBLP ] Energy Efficient Swing signal generation circuits for clock distribution networks. [Citation Graph (, )][DBLP ] A Voltage Controlled Nano Addressing Circuit. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.303secs