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Keh-Jeng Chang:
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Publications of Author
- C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:- [Conf]
- Norman H. Chang, Keh-Jeng Chang, John Leo, Ken Lee, Soo-Young Oh
IPDA: Interconnect Performance Design Assistant. [Citation Graph (0, 0)][DBLP] DAC, 1992, pp:472-477 [Conf]
- Keh-Jeng Chang, Soo-Young Oh, Ken Lee
HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs. [Citation Graph (0, 0)][DBLP] ICCAD, 1991, pp:294-297 [Conf]
- Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee
Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems. [Citation Graph (0, 0)][DBLP] ICCD, 1992, pp:184-189 [Conf]
- Martin G. Walker, Keh-Jeng Chang, Christophe J. Bianchi
SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters? [Citation Graph (0, 0)][DBLP] VLSI, 1999, pp:649-658 [Conf]
- Li-Fu Chang, Keh-Jeng Chang, Robert Mathews
Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects. [Citation Graph (0, 0)][DBLP] ISPD, 2000, pp:117-120 [Conf]
- Li-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi
A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance. [Citation Graph (0, 0)][DBLP] ISQED, 2000, pp:375-378 [Conf]
- Keh-Jeng Chang
Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability. [Citation Graph (0, 0)][DBLP] IWSOC, 2004, pp:219-222 [Conf]
- Li-Fu Chang, Abhay Dubey, Keh-Jeng Chang, Robert Mathews, Ken Wong
Incorporating Process Induced Effects into RC Extraction. [Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:12-17 [Conf]
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM. [Citation Graph (, )][DBLP]
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