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Vijay Pitchumani:
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Publications of Author
- Zerksis D. Umrigar, Vijay Pitchumani
An Experiment in Programming with Full First-Order Logic. [Citation Graph (1, 0)][DBLP] SLP, 1985, pp:40-47 [Conf]
- C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:- [Conf]
- Vijay Pitchumani
Embedded tutorial I: design for manufacturability. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:- [Conf]
- S. Ganguly, Vijay Pitchumani
Compaction of a Routed Channel on the Connection Machine. [Citation Graph (0, 0)][DBLP] DAC, 1989, pp:779-782 [Conf]
- Vinod Narayanan, Vijay Pitchumani
A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP] DAC, 1989, pp:734-737 [Conf]
- Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic
Variation-aware analysis: savior of the nanometer era? [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:411-412 [Conf]
- Vijay Pitchumani, Pankaj Mayor, Nimish Radia
A System for Fault Diagnosis and Simulation of VHDL Descriptions. [Citation Graph (0, 0)][DBLP] DAC, 1991, pp:144-150 [Conf]
- Mehmet Emin Dalkiliç, Vijay Pitchumani
Optimal Operation Scheduling Using Resource Lower Bound Estimations. [Citation Graph (0, 0)][DBLP] EDAC-ETC-EUROASIC, 1994, pp:319-324 [Conf]
- Mehmet Emin Dalkiliç, Vijay Pitchumani
A Multi-Schedule Approach to High-Level Synthesis. [Citation Graph (0, 0)][DBLP] ICCD, 1994, pp:572-575 [Conf]
- Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. [Citation Graph (0, 0)][DBLP] ISCAS (6), 2005, pp:6230-6233 [Conf]
- M. Kemal Unaltuna, Vijay Pitchumani
Quadrisectioning Based Placement with a Normalized Mean Field Neural Network. [Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:2047-2050 [Conf]
- M. Kemal Unaltuna, Vijay Pitchumani
A Stochastic Reward & Punishment Neural Network Algorithm for Circuit Bipartitioning. [Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:181-184 [Conf]
- M. Kemal Unaltuna, Vijay Pitchumani
ANSA: A New Neural Net Based Scheduling Algorithm for High Level Synthesis. [Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:385-388 [Conf]
- Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng
Integrating dynamic thermal via planning with 3D floorplanning algorithm. [Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:178-185 [Conf]
- Vinod Narayanan, Vijay Pitchumani
: A Parallel Algorithm for Fault Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP] ITC, 1988, pp:89-93 [Conf]
- Vijay Pitchumani, Pankaj Mayor, Nimish Radia
Fault Diagnosis using Functional Fault Models for VHDL descriptions. [Citation Graph (0, 0)][DBLP] ITC, 1991, pp:327-337 [Conf]
- Neeta Ganguly, Vijay Pitchumani
HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation. [Citation Graph (0, 0)][DBLP] VLSI Design, 1994, pp:175-178 [Conf]
- Vijay Pitchumani, Pankaj Mayor, Nimish Radia
A VHDL Fault Diagnosis Tool Using Functional Fault Models. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 1992, v:9, n:2, pp:33-41 [Journal]
- Mehmet Emin Dalkiliç, Vijay Pitchumani
Multi-schedule design space exploration: an alternative synthesis framework. [Citation Graph (0, 0)][DBLP] Integration, 1999, v:27, n:2, pp:87-112 [Journal]
- Vijay Pitchumani, Edward P. Stabler
An Inductive Assertion Method for Register Transfer Level Design Verification. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1983, v:32, n:12, pp:1073-1080 [Journal]
- Vijay Pitchumani, Edward P. Stabler
Verification of Register Transfer Level Parallel Control Sequences. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1985, v:34, n:8, pp:761-765 [Journal]
- Vijay Pitchumani, Satish S. Soman
Functional Test Generation Based on Unate Function Theory. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1988, v:37, n:6, pp:756-760 [Journal]
- Vijay Pitchumani, Qisui Zhang
A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:497-502 [Journal]
- Zuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:325-345 [Journal]
Who solves the variability problem? [Citation Graph (, )][DBLP]
A Hitchhiker's Guide to the DFM Universe. [Citation Graph (, )][DBLP]
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