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Roberto Suaya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
    Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  2. Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya
    A Two-Dimensional Topological Compactor With Octagonal Geometry. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:727-731 [Conf]
  3. Rafael Escovar, Roberto Suaya
    Transmission line design of clock trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:334-340 [Conf]
  4. Salvador Ortiz, Roberto Suaya
    Fullwave volumetric Maxwell solver using conduction modes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:13-18 [Conf]
  5. Rafael Escovar, Salvador Ortiz, Roberto Suaya
    Mutual inductance extraction and the dipole approximation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:162-169 [Conf]
  6. Salvador Ortiz, Roberto Suaya
    Efficient implementation of conduction modes for modelling skin effect. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:500-505 [Conf]
  7. Rafael Escovar, Salvador Ortiz, Roberto Suaya
    An improved long distance treatment for mutual inductance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:783-793 [Journal]
  8. Rafael Escovar, Roberto Suaya
    Optimal design of clock trees for multigigahertz applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:329-345 [Journal]
  9. John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya
    Two-dimensional IC layout compaction based on topological design rule checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:3, pp:260-275 [Journal]
  10. Rafael Escovar, Salvador Ortiz, Roberto Suaya
    Mutual inductance between intentional inductors: closed form expressions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  11. High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. [Citation Graph (, )][DBLP]


  12. Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. [Citation Graph (, )][DBLP]


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